Publications

Recent Highlight Publications

Pepe D. et al,

“A 78.8-92.8 GHz 4-bit 0-360° Active Phase Shifter in 28nm FDSOI CMOS with 2.3 dB Average Peak Gain”,

Accepted for publication at IEEE European Solid State Circuits Conference (ESSCIRC), 2015

Ossieur P., et al,

“A 1V 2mW 17GHz Multi-Modulus Frequency Divider Based on TSPC Logic Using 65nm CMOS”,

IEEE European Solid State Circuits Conference (ESSCIRC), 2014

Kennedy M., et al.,

“0.3-4.3 GHz Frequency-Accurate Fractional-N Frequency Synthesizer with Integrated VCO and Nested Mixed-Radix Digital Delta-Sigma Modulator-Based Divider Controller”,

IEEE Journal of Solid State Circuits (JSSC)

Brandonisio F., et al,

“Noise-Shaping All-Digital Phase-Locked Loops: Modeling, Simulation, Analysis and Design”,

Springer Book, Jan. 2014

Ossieur P., et al,

“A 10Gb/s Linear Burst-Mode Receiver in 0.25um SiGe:C BiCMOS”,

IEEE Journal of Solid State Circuits (JSSC), Feb 2013

Kennedy M., et al.,

“High Speed, High Accuracy Fractional-N Frequency Synthesizer using Nested Mixed-Radix Digital Sigma-Delta Modulators”,

IEEE European Solid State Circuits Conference (ESSCIRC), 2013

Other Publications

K. Sadeghipour et al,

“Design of a Sample-and-Hold Analog Front End for a 56Gb/s PAM-4 Receiver Using 65nm CMOS”,

International Symposium on Circuits and Systems (ISCAS) 2015

Mooney J. et al,

“Dithered Multi-Bit Sigma-Delta Modulator Based DPWM for DC-DC Converters”,

IEEE Applied Power Electronics Conference APEC 2015

Halton M. et al,

“Robust Analysis and Synthesis Design Tools for Digitally Controlled Power Converters”,

IEEE Applied Power Electronics Conference APEC 2015

Iordanov P. et al,

“Computation of the Real Structured Singular Value via Pole Migration”,

Int. Journal of Robust and Nonlinear Control, 2015

Zhu A. et al,

“Simplified Volterra Series Based Background Calibration for High Speed High Resolution Pipelined ADCs”,

IEEE MWSCAS 2015

Pepe D. et al,

“32 dB Gain W-band LNA in 28 nm Bulk CMOS”,

ICECS 2014

Effler S., et al,

“Scalable Digital Power Controller with Phase Alignment and Frequency Synchronization”,

IEEE Transactions on Circuits and Systems I (TCAS-I), 2014

Pepe D. et al,

“32 dB Gain W-band LNA in 28 nm Bulk CMOS”,

IEEE Microwave and Wireless Component Letters, 2014

N.A. Quadir, et al,

“An inductorless linear optical receiver for 20Gbaud/s (40Gb/s) PAM-4 modulation using 28nm CMOS”,

International Symposium on Circuits and Systems (ISCAS’2014), Melbourne, Australia, June 2014

Kennedy M. et al,

“A high frequency ‘divide-by-odd number’ CMOS LC injection-locked frequency divider”,

journal of Analog Integrated Circuits and Signal Processing, Springer, October 2013

Merini L. et al,

“Analyses and Design of 95-GHz SoC CMOS Radiometers for Passive Body Imaging”,

accepted for publication in the journal of Analog Integrated Circuits and Signal Processing, Springer.

Mooney J., et al,

“Application-Specific Instruction-Set Processor for Control of Multi-Rail DC-DC Converter Systems”,

IEEE Transactions on Circuits and Systems I (TCASI), January 2013

Wang N. et al,

“3-D Power Supply in Package enabled by high frequency, silicon-based, micro-magnetic Inductors”,

in proceedings of IEEE Electronic Components and Technology Conference (ECTC), 2013

Scharrer M., et al,

“Efficient Bi-directional Digital Communication Scheme for Isolated Switch Mode Power Converters”,

IEEE Transactions on Circuits and Systems I (TCASI), December 2012

Quadir N., et al,

“A 56Gb/s PAM-4 VCSEL driver circuit”,

Irish Systems and Signals Conference (ISSC), June 2012

Iordanov P., et al,

“Discrete-time Modelling and Robust Analysis of a Buck Converter”,

in Proceedings of the 7th IFAC Symposium on Robust Control Design (ROCOND), June2012

Keady A., et al,

“12 MHz to 5800 MHz Fully Integrated, Dual Path Tuned, Low Jitter, LC-PLL Frequency Synthesizer,”

in Proceedings of IET Irish Signals and Systems Conference (ISSC), 2012

Mereni L., et al,

“Feasibility Study Including Detector Non-Idealities of a 95-GHz CMOS SoC Radiometer for Passive Imaging”,

in proceedings of IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012

Merini L., et al,

“Feasibility and Challenges of a 95-GHz SoC Radiometer for W-Band Passive Imaging, “

in Proceedings of IET Irish Signals and Systems Conference (ISSC), 2012

Awan M., et al,

“A “Divide-by-Odd Number” Direct Injection CMOS LC Injection-Locked Frequency Divider”,

in proceedings of IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012

Mullane B., et al,

“A high performance band-pass DAC architecture and design targeting a low voltage silicon process”,

in Proceedings of IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2011

Mullane B., et al,

“A 100dB SFDR 0.5V pk-pk band-pass DAC implemented on a Low Voltage CMOS Process”,

Book Chapter, VLSI-SoC: The Advanced Research for Systems on Chip, VLSI-SoC 2011 Revised Selected Papers, 2012

O’Brien V., et al,

“High order mismatch noise shaping for bandpass DACs,”

in Proceedings of IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2011

Collins D., et al,

“Fast Digital Calibration of Static Phase Offset in Charge-Pump Phase-Locked Loops”,

in Proceedings of IET Irish Signals and Systems Conference (ISSC), 2011

Hannon J., et al,

“Design of a DC-DC Converter with Co-Packaged Inductor”,

in Proceedings of IEEE International Workshop on Power Supply On Chip, (PowerSoC), 2010