Distinguished Lecture by Feng-Wei Kuo of TSMC

We are delighted to be hosting a Distinguished Lecture Talk with Feng-Wei Kuo of TSMC.

He will present on  “Mixed-Signal Circuits for IoT and 4G Mobile Transceivers”

On Friday Aug 31st at 12noon in UCD School of Engineering


In this talk, I will give an overview of my group’s research program at TSMC on circuits and device innovation for future low-power and high-performance electronics. The topics include several unconventional Bluetooth low energy (BLE) transceivers and all-digital PLL (ADPLL) architectures developed by TSMC in collaboration with University College Dublin (UCD) and Delft University of Technology (TU Delft). First, a BLE transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with a switched current-source digitally controlled oscillator (DCO) featuring low frequency pushing, and class-E/F2 digital power amplifier (PA), featuring high efficiency. Second, the BLE receiver operates in discrete time at high sampling rate (∼10 Gsamples/s) with intermediate frequency placed beyond 1/ f noise corner of MOS devices. New multistage multi-rate charge-sharing band-pass filters are adapted to achieve high out-of-band linearity, low noise, and low power consumption. Third, an integrated on-chip matching network serves to both PA and low-noise trans-conductance amplifier, thus allowing a 1-pin direct antenna connection with no external band-selection filters. Fourth, an ultra-low-voltage (ULV) transmitter (TX) / receiver (RX) powered from a single 0.5V / 0.275V supply. Finally, a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios that is optimized for advanced CMOS. It is based on a 1/8-length TDC of stabilized 7 ps resolution, as well as wide tuning range, fine-resolution class- F DCO with only switchable metal capacitors. This can not only achieve high performance and be scaling friendly, but also be fully synthesizable using standard digital flow, greatly improving productivity.


Speaker Biography:

Mr. Kuo received the M.S. degree in electronics engineering form National Chiao Tung University, Hsinchu, Taiwan, R.O.C., Taiwan, in 2007. In 2007, he joined the Design Technology Division, Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan. His research interests include ultra-low power transceiver and digital/analog PLLs, delay-locked loops, and high-speed data-communication circuits design using advanced CMOS technology, as well as CMOS analog circuits. He has published more than 13 technical papers, and holds 65 granted U.S. patents. He is currently pursuing a Ph.D. degree at University College Dublin as an external part-time student.

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