PhD Researchers in PMIC Circuit Design for Real Time Control of Level and Multi-Stage Power Converters

  • Cork

MCCI is Ireland’s national Microelectronics Circuits Research Centre. Hosted by Tyndall Research Institute (, MCCI has a large team of researchers in silicon chip design, at various stages of their careers, from PhD researcher through to Principal Researcher and all are creating world leading, innovative and high impact technologies, which will shape our future lives. Specifically, MCCI’s mission is to carry out industry-driven, excellent research in areas such as Analog Precision Circuits, RF and High Speed Transceivers, Cryogenic CMOS and Integrated Power Systems research.

Analog Devices Inc. (ADI) is the world’s largest Integrated Device Manufacturer (IDM) in the power management field. Analog Devices is sponsoring this prestigious PhD research scholarships in CMOS Power Control ICs, based at MCCI’s office at Tyndall National Institute Cork Ireland. Power and energy control are now defining the fundamental performances achievable in every single electronic system, from the RF powered medical implant through to the AI accelerator in the data-centre server. The role will position the researcher at technology curve edge and be valuable to a diverse range of career areas in power management or IC design.

The Research Area

Generally, the power systems in every electronics hardware system or device are undergoing a number of major technology paradigm shifts, which is making power control central to achieving the continued performance improvements, which we expect in this “more than Moore” era.

From the grid AC electricity connection to the end application, there are typically five stage of power conversion. Powering architectures, such as those being architected through the Open Compute Project are changing so that end-to-end efficiency can be pushed into the high eighties, per cent. AT no-load standby and lighter loads, the goal is to design control modes so that every stage maintains maximum efficiency and minimum quiescent control power. The key application SoC, ASIC, CPU, MCU, AI Accelerator or GPU in every application is moving to a very fine geometry CMOS node with high digital gate leakage. The last stage of power conversion – the VR voltage regulator – is becoming highly integrated and splitting into hundreds of highly dynamic rails, which power application CMOS circuit blocks on and off precisely as required to implement fine-grained power delivery. Driving this trend for a huge number of last-stage highly dynamic rails, also, is the tendency for applications to go multi-core – presently eight cores for a mobile phone and hundreds of cores in a computer server. These highly integrated rails deliver up to 20 A/ns and having very little local input decoupling (reservoir) capacitance, they push are pushing the requirement for high dynamic performance up-stream to other stages in the powering architecture, such as the 48 V – 5/12 V DC-DC modules. These modules, in themselves have recently migrated from 12 V input to 48 V input, to reduce distribution current RI2 power loss in system PCB traces. To “break” this voltage or converter it through a large down conversion ratio, there are a variety of emerging new multi-stage topologies combining switched capacitor stages with traditional switch-mode inductor based stages. These new power topologies are achieving very high efficiencies and with their cascade of smaller inductor and capacitor energy storage elements, have the as yet, unrealised potential to achieve very high dynamic performances. These complimentary PhD research themes are specifically about innovating in the power control and management ICs for DC-DC converters, specifically with the goals of bringing high dynamic performance to hybrid multi-stage, multi-level flying capacitor (FCML) or hybrid resonant switched capacitor (ReSC) DC-DC converter.

Controllers required

Traditionally, switch mode converter controllers have been voltage-mode or current mode and have been classical PID or PI, respectively to control state-space averaged linear time invariant (LTI) system representations. There have been analog and digital (discrete time) versions. These systems achieve closed-loop control over the load voltage, dynamic set-point tracking and maintain fixed switching frequency for output noise spectrum control, but at the expense of high bandwidth ADCs, amplifiers and modulators. The challenges of achieving fast transient responses, high efficiency over load, lower CMOS complexity and area implementations resulted in a variety of non-linear hysteretic controllers, with varieties of constant on-time (COT), fixed-off time (FOT), adaptive on-time AOT, according to achieve various goals such as good line rejection. These controllers achieve lower cost implementations but have the drawbacks of variable switching frequency and some unpredictable output voltage ripples. More recently linear controllers are emerging which show promise with implementing time domain controllers using time, instead of voltage as the processed signal, using voltage controlled oscillators (VCOs) and voltage controlled delay lines (VCDLs).

Suggest PhD Research Matter

High dynamic performance controller for multi-level, multi-stage FCML or ReSC. It is anticipated that a monolithic multi-level converter with high performance mixed-signal controller will be created. The controller will incorporate the best elements of today’s non-linear, linear time invariant (LTI) and discrete time (DTLTI) control techniques to achieve accurate, highly dynamic, competitive CMOS area and highly efficient power control over all loads.

The research goal is to focus on the highest possible bandwidth control, with accuracy and dynamic performance appropriate for last stage VR controllers. The goal is to combine the best attributes of functionality implementations from the variety of control schemes to realise high performance control with low cost, low area digital type CMOS implementations which are substantially auto-synthesisable and transferrable across CMOS geometries and maintain over-load efficiency and generate controlled noise spectra. The dynamic performances achieved will be appropriate fine geometry CMOS SoCs requiring low core voltages (~ 0.4 V) but with very tight regulation accuracy and features such as DVFS.

What we offer

  • You will have the opportunity to pursue your research to the highest level in a world-class CMOS technology design center that has a young, dynamic, vibrant and self-driven research environment. You will be part of a large, collegial and supportive team of researchers at all levels of experience and across a variety of relevant disciplines, such as thin-film magnetics, signal processing and data-converters.
  • There will be a 6-month internship at Analog Devices Ireland Design Centre Office at the beginning of the PhD period.
  • There is an excellent research environment, which is co-located with many world leading research groups, such as Tyndall’s Integrated Magnetics group. Tyndall Research Institute and MCCI together host over 500 researchers, with approximately 150 pursuing PhD research.
  • These PhD research themes are of strong strategic relevance to the sponsoring company and as such there will be access to company expertise, through means such as internal corporate technical conferences or internship at an ADI site.
  • Great career development and advancement that is highly visible to the semiconductor industry through direct contact with the sponsoring company, other MCCI member companies’ base and through IEEE publications and conferences.
  • Opportunities to publish and present at the leading conferences such as IEEE Solid-State Circuits conferences will be very strongly supported and indeed will be your primary focus
  • Attend training courses and workshops, use the latest industry CAD design tools
  • A generous tax-free scholarship payment per year including University college PhD fees
  • Excellent researching conditions

Key Responsibilities

  • Complete your PhD research degree in high dynamic performance, real-time CMOS power management (PMIC). Your research will significantly advance the state-of-the-art from both research and commercial perspectives
  • Complete mixed-signal PMIC integrated circuit prototypes (“test chips”) from concept, circuit design through silicon layouts, tape-out and silicon test characterization in the Design evaluation labolatory. These test chips will implement a complete integrated switch-mode power system including power path, gate drives and control, to showcase the noteworthy advancements made by your research
  • Perform experimental test characterisation of your stand-alone prototype PMIC test chips to showcase your advances in mixed-signal, high dynamic performance, real time power control as applied to select power topologies
  • Author or co-author peer-reviewed publications of international standing
  • Engage in the dissemination of the results of the research, in other fora, as directed by and with the support of senior MCCI research staff. There will be presentations for in-house and company internal conferences.
  • Manage/participate in education and public outreach engagement activities, as required
  • Ensure all activities are compliant with MCCI Processes and the Tyndall Quality Management System
  • Carry out any additional duties as may reasonably be required within the general scope and level of the post

About You     

  • You will be ambitious to achieve a high quality research PhD through publications in pre-eminent tier 1 conferences and journals from University College Cork
  • You plan committing to a strong technical career in the area of power management with advanced digital control

Essential Criteria

  • The ideal applicant will have a 1st class honours degree in electronic engineering or related discipline
  • Evidence of a strong desire to innovate and pursue advanced research
  • Evidence of being highly analytical, with good interpersonal and organisational skills
  • Strong fundamental knowledge in core disciplines such as engineering mathematics, analog circuits, control systems theory and power electronic systems
  • Strong technical writing and communications skills

Desirable Criteria

  • Masters Degree in a relevant research area in electronics
  • Specialised modules at under-graduate level in CMOS IC design, power electronics, control system design or digital signal processing
  • Good understanding of switch-mode converter design and magnetic component operation
  • Good understanding of continuous and discrete time controller design methodologies
  • Experience with mixed-signal IC design
  • Experience with mathematical modelling tools, such as MATLAB or Python
  • Experience with integrated circuit design tools, such as Cadence/ Mentor

To have a chat or make an informal enquiry, in confidence, please feel free to contact or

The annual stipend is €22,000 pa. In addition, yearly University academic fees will paid by the Tyndall National Institute.

The closing date for applications is 21st June, 2024.

To apply for this job please visit