Principal CMOS Researcher/ Designer in Mixed-Signal Energy-Harvesting PMIC

  • Cork

MCCI is Ireland’s national Microelectronics Circuits Research Centre. MCCI has a team of over 90 researchers and engineers hosted across Tyndall National Institute (, UL, SETU Carlow and UCD, collaborating on more than 50 research projects. Funded by Enterprise Ireland and IDA Ireland, its focus is to generate innovative technologies, which create high impact. Specifically, MCCI’s mission is to carry out industry-led, excellent Analog, Mixed-Signal, RF and Power Management Integrated Circuit research.

As part of its Ultra-Low power, Mixed-Signal, Energy-Harvesting PMIC research theme, MCCI offers this Principal Researcher/ Designer opportunity at its Tyndall National Institute based Cork office.

The Research Area

Our focus is on researching techniques to bring advanced mixed-signal control features to the sub-µW, energy-harvesting, smart sensing node’s power management IC (PMIC) space. Research PMICS derived from the Tyndall multiple-source, energy-harvesting PMIC platform will enable many of the edge nodes in tomorrow’s internet-of-things, IoT, to become battery-less by efficiently harvesting available ambient energies and supporting a reduction in the system’s energy consumption. Body-wearable and inductively powered, implantable medical devices are additional target application areas. This platform will also be at the heart of highly integrated energy-source in-package (eSiP) systems designed to showcase technologies being created across Tyndall’s co-located research groups, in areas such as thin-film magnetic-on-silicon, III-V UV PV devices, solid-state electrochemical storage cells/sensors and MEMS scale energy harvesting transducers spanning thermoelectric (TEG), PV or piezo/ electromagnetic vibrational.

About The Role

The role will ideally suit the established academic PMIC Researcher or industry based Principal CMOS Designer or Design Group lead who desires a career path transitioning into research leadership in the Ultra-Low Power Energy Harvesting PMIC area.

You will be the central CMOS design person in the group’s existing mixed-signal, flexible, ultra-low-power platform, so that it will support the creation of derivative research PMICs across the entire ultra-low power energy harvesting application space, employing low voltage DC thermoelectric (TEG), PV, RF and low voltage AC vibrational.

Reporting to the Head of Group, you will act as both an independent design contributor and will support with guiding a team of post-graduate research staff and PhD students.

About You     

You will be ambitious to attain a high profile research career through publishing and presenting at tier-one silicon conferences.

Key Responsibilities

  • Provide research stewardship support within MCCI’s ULP PMIC research theme to deliver excellent research that will deliver innovative and commercialisable technologies, intellectual property and key publications in pre-eminent journals and tier-1 international conferences.
  • Author, mentor and co-author peer-reviewed publications of international standing.
  • Build research partnerships and create research proposals, which will attract funding from both Industry and public research bodies in both Ireland and the European Union.
  • As an individual contributor, complete mixed-signal CMOS ULP PMIC circuit designs from concept through tape-out and silicon characterisation.
  • Model, design and simulate novel mixed-signal control systems to maximise energy transduction from a range of µW-level ambient energy harvester types including PV, TEG, and Piezo Vibrational, into both energy storage devices (supercapacitors and rechargeable cells) and to well-regulated system voltages.
  • Design, synthesise and validate ULP digital control blocks for CMOS to implement voltage, current, power and energy control loops for the above harvester types.
  • Create and validate analog layouts, as well as place & route and timing closure for digital circuits.
  • Perform experimental characterisations of stand-alone prototype ICs and in power converter systems.
  • Manage/participate in education and public outreach engagement activities, as required.
  • Ensure all activities are compliant with MCCI Processes and the Tyndall Quality Management System and required Health & Safety standards.
  • Carry out any additional duties as may reasonably be required within the general scope and level of the post.

Essential Criteria

  • Post Graduate Degree in Electronic Engineering or equivalent discipline
  • Significant track record of design and research leadership in Power Management IC (PMIC), Gate Driver IC , RF or Precision Mixed-Signal IC
  • Evidence of successful ownership and execution of high performance or innovative analog, digital, mixed-signal, PMIC or RF CMOS circuit designs from architecture through to tape-out
  • Evidence of strong team oriented management skills through stewarding a CMOS design or research team to develop innovative “break-through” IC circuits.
  • Record of guiding collaborations across organisations, functions and research or development teams
  • Broad based knowledge of switch-mode power converter topologies, energy harvesters, storage devices and magnetic devices
  • Evidence of strong capability in research proposal writing and research or project funding acquisition
  • The successful candidate will have very good interpersonal, communications and organizational skills
  • The successful candidate will have a significant tier-one publishing and/or patenting record

Desirable Criteria

  • PhD in Power Management IC (PMIC), Gate Driver, RF, Precision Mixed-Signal IC or related area
  • Experience in supervision of post-graduate students studying at Masters/ PhD level
  • Strong track record of securing platform design or research funding
  • Strong knowledge of digital control loop design
  • Experience of multi-domain mixed-signal systems level modelling in MATLAB-SIMULINK
  • Experience of the patenting process, IP management or technology transfer

To have a chat or make an informal enquiry, in confidence, please feel free to contact

The appointment may be made on the Admin I Grade 7 Salary Scale, €77,404 to €101,965 p.a. Salary placement on appointment will be in accordance with the public sector pay policy.

Closing date of applications  is 29th September, 2023

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