• A 180mV 81.2%-Efficient Switched-Capacitor Voltage Doubler for IoT using Self-Biasing Deep N-Well in 16-nm CMOS FinFET

    A 180mV 81.2%-Efficient Switched-Capacitor Voltage Doubler for IoT using Self-Biasing Deep N-Well in 16-nm CMOS FinFET

    Abstract: We introduce the first monolithic step-up dc-dc converter operating at deep sub-1V (i.e., 0.18–0.4 V) that outputs significant power for IoT with a peak power efficiency of 81.2% at 50 μ W output power for the 0.18V input, and 87.1% at 300 μ W output power for 0.4V. It is implemented in 16-nm FinFET CMOS and uses a MOS transistor as a high-density flying capacitor for energy conversion. The capacitor is arranged in a self-biased deep N-well topology, which enhances the overall efficiency by 9.5%. An integrated time-to-digital converter (TDC) verifies the dc–dc output quality.

    Bio: Naser Pourmousavian received the B.Sc. degree in electrical engineering from the Sharif University of Technology, Tehran, Iran, in 2012, the M.Sc. (cum laude) degree in Electrical Engineering from KU Leuven, Belgium, in 2014. He has been a PhD student at UCD since December 2014. In 2017, he was an interim engineering intern in Qualcomm, San Diego, where he was part of the RFIC design group. He was a recipient of the the ISSCC 2017 Student-Research-Preview Poster Award.

  • Passive Switched-Capacitor delta-sigma Modulator Based on Pipelined Charge-Sharing Rotation in 28-nm CMOS

    Passive Switched-Capacitor delta-sigma Modulator Based on Pipelined Charge-Sharing Rotation in 28-nm CMOS

    Abstract: In this paper, we introduce a new switched-capacitor (SC) passive delta-sigma (DS) modulator architecture. It is based on a charge-sharing rotation technique, which eliminates any inter-stage loading effects that plague the conventional SC passive DS modulators. To improve the proposed modulator’s noise suppression and stability, an independent extra feedback path and a zeroing stage are added to the 2nd-stage integrator. Moreover, a pipelining (i.e. interleaving) technique is employed in the passive low-pass filter to relax settling requirements and improve power efficiency. Compared to the DS modulators with active integrators, the proposed modulator contains only switches, capacitors and one comparator, thus being greatly amenable to nanoscale CMOS process nodes. Implemented in 28-nm CMOS, the proposed ADC occupies a core area of 0.059 mm2. It achieves measured SNDR of 81.1 dB and a measured dynamic range (DR) of 83.6 dB with a signal bandwidth of 80 kHz at 40.96 MS/s, while consuming 101.5 µW. SNDR is maintained above 70 dB across a ±20% supply variation.

     

    Bio: Hongying Wang received the B.Sc. and M.Sc. degrees in Microelectronics from Harbin Institute of Technology (HIT), Heilongjiang, China, in 2013 and 2015, respectively. Between 2015 and 2016, she was studying and carrying out research in biosensors at Hong Kong University of Science and Technology (HKUST), Hong Kong, China. She is currently pursuing the Ph.D. degree in Microelectronics at University College Dublin (UCD), Dublin, Ireland. During 2017, she worked as an IC design intern for three months at Qualcomm, Cambridge, UK. Since 2017, she has been a designer with a startup company Equal1 to build a single-chip CMOS quantum computer. Her current research interests include level-crossing-sampling ADCs, Delta Sigma ADCs and cryogenic circuit design.

  • Challenges in On-Chip Antenna Design and Integration with RF Receiver Front-End Circuitry in Nanoscale CMOS for 5G Communication Systems

    Challenges in On-Chip Antenna Design and Integration with RF Receiver Front-End Circuitry in Nanoscale CMOS for 5G Communication Systems

    Abstract: This talk presents design considerations and challenges of integrating on-chip antennas in nanoscale CMOS technology at millimeter-wave (mm-wave) to achieve a compact front-end receiver for 5G communication systems. Solutions to overcome these challenges are offered and realized in digital 28-nm CMOS. A monolithic on-chip antenna is designed and optimized in the presence of rigorous metal density rules and other back-end-of-the-line (BEoL) challenges of the nanoscale technology. The proposed antenna structure further exploits ground metallization on a PCB board acting as a reflector to increase its radiation efficiency and power gain by 37.3% and 9.8 dB, respectively, while decreasing the silicon area up to 30% compared to previous works. The antenna is directly matched to a 2-stage LNA in a synergetic way as to give rise to an active integrated antenna (AIA) in order to avoid additional matching or interconnect losses. The LNA is followed by a double-balanced folded Gilbert cell mixer, which produces a lower intermediate frequency (IF) such that no probing is required for measurements. The measured total gain of the AIA is 14 dBi. Its total core area is 0.83 mm2 while the total chip area, including the pad frame, is 1.55×0.85 mm2.

    Bio: Mahsa Keshavarz Hedayati received the B.Sc., M.Sc., and Ph.D. degrees in electrical and electronics engineering from the Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran, in 2008, 2011, and 2018, respectively. She was a Teacher Assistant and an Instructor with the Amirkabir University of Technology and Azad University at Qazvin, from 2012 to 2015. In 2015, she joined the Analog, RF and Mixed-Signal Research Group, University College Dublin (UCD), Dublin, Ireland, as a Visiting Ph.D. Student Researcher. Since 2018, she has been an RFIC Design Engineer with Decawave, Dublin, Ireland. Her research interests include RFIC design, integrated on-chip antennas, and RF/millimeter-wave (mm-wave) CMOS transceivers. She was a Winner of the Best Student Paper Bronze Award of the IEEE Asia-Pacific Conference on Applied Electromagnetics (APACE 2010) and the Best Poster Silver Award at IEEE Solid-State Circuits Society MCCI annual forum, Cork, Ireland (Oct. 2016).

     

  • A 0.5 V 1.6 mW 2.4 GHz Fractional-N All-Digital PLL for Bluetooth LE with PVT-Insensitive TDC using Switched-Capacitor Doubler in 28 nm CMOS

    A 0.5 V 1.6 mW 2.4 GHz Fractional-N All-Digital PLL for Bluetooth LE with PVT-Insensitive TDC using Switched-Capacitor Doubler in 28 nm CMOS

     

    Abstract: This work proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5V supply. While its DCO runs directly at 0.5V, a switched-capacitor DC-DC converter doubles the supply voltage to all the digital circuitry and regulates the TDC supply to stabilize its resolution thus maintaining fixed in-band phase noise (PN) across PVT. The ADPLL supports a 2-point modulation and forms a Bluetooth LE (BLE) transmitter realized in 28 nm CMOS. It achieves in-band PN of -106 dBc/Hz (FoM of -239.2 dB) and RMS jitter of 0.86 ps while dissipating only 1.6mW at 40MHz reference. The power consumption reduces to 0.8mW during BLE transmission when the DCO switches to open-loop.

     

    Bio: Naser Pourmousavian received the B.Sc. degree in electrical engineering from the Sharif University of Technology, Tehran, Iran, in 2012, the M.Sc. (cum laude) degree in Electrical Engineering from KU Leuven, Belgium, in 2014. He has been a PhD student at UCD since December 2014. In 2017, he was an interim engineering intern in Qualcomm, San Diego, where he was part of the RFIC design group. He was a recipient of the the ISSCC 2017 Student-Research-Preview Poster Award.

  • Quantum Bits (Qubits) Implemented through Electrostatically Coupled Quantum Dots in Nanometer-Scale CMOS

    Quantum Bits (Qubits) Implemented through Electrostatically Coupled Quantum Dots in Nanometer-Scale CMOS

    Abstract: Considering the enormous advances in nanometer-scale CMOS technology that now allows one to reliably fabricate billions of switching devices on a single silicon die, electrostatically controlled quantum dots appear to be promising candidates for a batch implementation of quantum bits (qubits) and quantum logic circuits in order to facilitate mass production of quantum computers. This talk introduces the concept of semiconductor qubits and discusses the feasibility of such qubits from the point of view of quantum information and from the point of view of practical implementation. 

    We begin by explaining the idea of classic and quantum bits of information and highlighting the difference between the two. We then show what quantum systems can be qualified as qubits. Using the framework of the Schrodinger formalism, we develop a theoretical approach and simulation techniques to understand the behaviour of electrons injected in quantum dots, and, hence, the dynamics of semiconductor qubits. We introduce the fidelity of a semiconductor qubit and construct its Bloch sphere.  Finally, we conclude the talk by presenting a discussion on universal quantum gates realised through such semiconductor qubits. 

    Bio: Dr. Elena Blokhina received the Habilitation HDR (D.Sc.) degree in electronic engineering from UPMC Sorbonne Universities, France, in 2017, a Ph.D. degree in physical and mathematical sciences and an M.Sc. degree in physics from Saratov State University, Russia, in 2006 and 2002 respectively. Since 2007, she has been with the School of Electrical and Electronic Engineering of University College Dublin, Ireland, and is currently a lecturer and the coordinator of the Circuits and Systems Research Group. Dr Blokhina is a Senior member of IEEE and the Chair Elect of the IEEE Technical Committee on Nonlinear Circuits and Systems. She had been elected to serve as a member of the Boards of Governors of the IEEE Circuits and Systems Society (CAS) for the term 2013-2015 and has been re-elected for the term 2015-2017.  She has served as a member of organising committees, review and programme committee, session chair and track chair at many international conferences on electronics, circuits and systems and nonlinear physics including as IEEE International Symposium on Circuits and Systems (ISCAS), IEEE Latin American Symposium on Circuits and Systems (LASCAS), IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), International Symposium on Nonlinear Theory and Its Applications (NOLTA),  IEEE international Conference on Electronics, Circuits and Systems (ICECS) and others. Dr Blokhina has served as a founder and the Programme Chair of the first edition of IEEE Next Generation of Circuits and Systems Conference (NGCAS) 2017 and of IEEE ICECS 2018. In 2016-2017 Dr Blokhina was an Associate Editor for IEEE Transactions on Circuits and Systems I, and since 2018 she is the Deputy Editor in Chief of that Journal. Her research interests include the analysis, design, modelling and simulations of circuits, systems and interfaces with physical sub-systems with a particular focus on emerging applications. She has led or participated a number of projects in the area of MEMS, NEMS and micro-scale energy harvesting, distributed frequency synthesis, time series prediction on chip and interfaces with quantum devices. 

     

  • GaN MMIC PAs for 5G

    GaN MMIC PAs for 5G

    Abstract: In this talk, we present innovations in GaN MMIC power amplifiers (PAs) for 5G wireless networks. First, a design approach is proposed to embed a “minimum-inductance” bandpass filter into output matching network of the PA, to achieve low in-band insertion loss and high harmonic suppression. We present a linearization technique using the compressive and expansive nonlinearity profiles of transistors’ transconductance and gate-source capacitance, compensating for the AM-PM distortion of the PA. Moreover, a transformer-based load modulation network is proposed for bandwidth enhancement of integrated Doherty PAs. Finally, we present the unbalanced PA, a novel architecture developed for broadband back-off efficiency enhancement.

    Bio: Reza Nikandish received the PhD degree in Electrical Engineering from the Sharif University of Technology, Tehran, Iran. He is a Research Fellow at University College Dublin, Ireland. His current research interests include RF and mm-wave integrated circuits for 5G communications and CMOS quantum computing.

     

  • A Low Power, Low Noise, 1V Supply Dynamic Comparator Pre-amplifier in 65nm CMOS Process

    A Low Power, Low Noise, 1V Supply Dynamic Comparator Pre-amplifier in 65nm CMOS Process

     Abstract: This talk presents a low power dynamic pre-amplifier architecture for Comparators. The prototype is designed in a 65nm CMOS process with supply voltage of 1V and is compared against the widely used double tail latch comparator in terms of power consumption, input referred noise and speed. Adding a cross-coupled mechanism to the input differential pair prevents the output nodes from fully discharging. This reduces the power consumption while achieving similar noise levels with a minimal increase to the conversion time. The proposed circuit achieves input referred rms noise of voltage of 220uV against 210uV of standard pre-amplifier architecture with 30% reduction in power. The proposed circuit consumes 0.19pJ per comparison.

    Bio: Subhash Chevella is a PhD Student at MCCI, Tyndall National Institute, Cork. He received his Master of Technology in Information & Communication Technology in 2011 from DAIICT, Gandhinagar, India, and Bachelors of Technology in Electronics and Communication Engineering in 2009 from JNTU, Hyderabad, India. He joined MCCI in 2017 with over 6 years of industry design experience and is focused on high precision ADCs and Digitally Assisted techniques to improve performance for Low noise, High Speed Dynamic Amplifiers. His research interests are in investigating techniques to improve linearity and noise in Analog Engineering blocks, calibration mechanisms for Dynamic Amplifiers, Comparators, Analog & Mixed Signal Integrated Circuits, Continuous Time Data Converters, and Low Power Differential Amplifiers.

     

  • 14-bit 1MS/s Ultra-low Power SAR ADC Targeting 1fJ/Conv Operating at 1V and 500mV Supply in 65nm CMOS Process

    14-bit 1MS/s Ultra-low Power SAR ADC Targeting 1fJ/Conv Operating at 1V and 500mV Supply in 65nm CMOS Process

    Abstract: This talk presents a 14-bit 1MS/s ultra-low power SAR ADC targeting 1FJ/conversion. Two versions of a 14-bit ADC were taped out on the same die, with supply voltage of 1V and 500mV. The prototype is designed in a 65nm CMOS process. This work aims to reduce the power in a SAR ADC by reducing the supply voltage from 1V to 0.5V in standard 65nm without any reduction in performance. One additional bit of resolution when approaching the KT/C noise limit, leads to 4x larger capacitance, with an equivalent increase of power consumption. Therefore, maintaining very low FOM with increasing ENOB is quite challenging and definitely not straightforward. Meanwhile most comparator architectures stop working once the supply voltage reduces below approximately 700-800 mV. This talk proposes an alternative approach to this challenge by employing voltage boosting technique and switching the supply voltage.

    Bio: Madhan Venkatesh is currently working towards a PhD degree at MCCI, Tyndall National Institute, Cork. He received his Bachelor’s degree in Electronics and Communication Engineering in Visvesvaraya Technological University, Karnataka, India in 2015. Prior to his PhD studies he completed an internship in Indian Statistical Institute – Bangalore. His current research focus is on low power and low voltage analog to digital converters, comparators, analog and mixed signal ICs, and low power digital circuits.

  • A precision noise shaped SAR: Design trade-offs, measured results and debug

    A precision noise shaped SAR: Design trade-offs, measured results and debug

    Since the introduction of 90nm CMOS, Successive Approximation Register (SAR) ADCs have become the dominant low power ADC architecture. However, the best performing ADCs from a power consumption point of view have 10 bits of resolution and a signal bandwidth of <1MHz. The key blocks in SAR ADCs are capacitors, comparators, timing logic and processing logic which all benefit from faster CMOS technologies. This work aims to leverage such speed advantage through oversampling and noise shaping to achieve an ADC with greater precision.

     

    Bio: Daniel O’Hare received the BE degree in Electronic Engineering from University College Dublin in 2000 and completed his PhD at the University of Limerick in 2017. He joined Motorola Semiconductor in 2000 and from 2004 to 2008 he was with Freescale Semiconductor designing ADCs and DACs for cellular transceivers. From 2008 to 2012 he was Analogue Design Lead with M4S NV a spinout of IMEC and from 2013 to 2017 he was an ADC researcher in the Circuits and Systems group at the University of Limerick. Since 2017 he is a Senior Researcher at MCCI based in the Tyndall National Institute. He lectures “Advanced Analog IC Design” to UCC Masters in Electronic Engineering students. Danny’s current research is in precision ADCs and low-noise sensor interface circuits. He is design lead/architect of the MCCI “Precision Noise-shaped SAR” project. He is also supervising Postgraduate research projects investigating precision current interfaces capable of detecting currents with pico-ampére precision. He has several on-going projects with the Bio-photonics group at Tyndall National Institute. Danny’s research interests are low noise, area and voltage analogue interface circuits and ADCs. These interests are applied in Sensor interface ICs with precision current sensing interfaces a strong interest.

     

    Bio: Gerardo Molina Salgado received the B.S., M.S and Ph.D. degrees in Electronics Engineering from Institutes ITP and INAOE (Mexico), in 2009, 2011 and 2015, respectively. During his Ph.D. studies, he joined the Microelectronics Institute of Seville (IMSE), Seville, Spain, and Texas A&M University, USA, as a visiting scholar. Since January 2016 he is working as a Postdoc Researcher at the Microelectronic Circuits Centre Ireland (MCCI) – Tyndall National Institute, Cork, Ireland. His research projects range from system level design, circuit design/verification, to silicon validation of state of the art Analog-to-Digital Converters (ADCs). He is currently developing novel high resolution ADC architectures using digital signal processing techniques to compensate for analog circuit imperfections. He is also continuously developing & improving his Matlab(R)-based SAR ADC design toolbox, SIMSAR, which provides accurate simulation results at a highly reduced computational time. The SIMSAR toolbox is available to download free of charge from https://www.mcci.ie/simsar-toolbox/. His main research interests are in Noise-Shaping SAR ADC, Sigma-Delta-Modulators, development of CAD tools for ADC design, and Multi-Rate Digital-Signal-Processing. He has also authored a number of technical papers in the aforementioned areas.

  • A Vertically Integrated RFDAC with Analog Linear Interpolation in 28-nm CMOS

    A Vertically Integrated RFDAC with Analog Linear Interpolation in 28-nm CMOS

    In this presentation, a wideband 2.4 GHz 2×9-bit Cartesian radio-frequency digital-to-analog converter (RFDAC) is demonstrated. Vertical integration is introduced in the physical implementation, where all key active circuitry is located underneath the matching-network transformer, achieving a core area of merely0.35 mm2. An 8×analog linear interpolation at the RF rate is proposed to suppress replicas close to the carrier while avoiding any high-order and high-speed digital filters in digital processing back-end. The multi-port transformer is adopted in the matching network to improve the back-off efficiency. The RFDAC operates across the 3-dB bandwidth from 1.8 to 2.8 GHz. The measured peak output power and drain efficiency at the center frequency of 2.4 GHz are 17.47 dBm and 17.6% respectively, while the peak efficiency is 19.03%. Moreover, the 6-dB back-off efficiency is at66% of that at the peak output power. The vertical integration helps this RFDAC to achieve the smallest area among comparable prior arts.

     

    Bio: Feifei Zhang received the B.Sc. of navigation guidance and control from Beijing University of Aeronautics and Astronautics and M.Sc. in micro-electronics in Beijing Embedded System Key Lab from Beijing University of Technology in 2014. She is currently pursuing a Ph.D. degree with University College Dublin, Dublin, Ireland. Her current research interests include radio frequency digital to analog converter.

  • A 15-μW, 103-fs Step, 5-Bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28nm CMOS

    A 15-μW, 103-fs Step, 5-Bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28nm CMOS

    Abstract: This work proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant discharging slope fed to a fixed-threshold comparator. The DTC operation mechanism is provided and design tradeoffs are investigated. The proposed DTC consumes only 15 uW from a 1 V supply, while achieving fine resolution of 103 fs clocking at 40 MHz. The measured INL and DNL are 0.73/0.35 LSB within a 5-bit range. The DTC achieves a figure-of-merit of 8.5 fJ, which appears the best among state-of-the-art.

    Bio: Peng CHEN received his BSc degree in Electronics from Huazhong University of Science and Technology, and MSc in Microelectronic from TU Delft, Delft, Netherlands, in 2012 and 2014 respectively (MSc thesis done at IMEC Holst Center in Eindhoven, NL).  From 2014-2015, he worked as a test manager for Huawei Technologies in Amsterdam. Since Sept. 2015, he has been a PhD student in University College Dublin supervised by Prof. Bogdan Staszewski. He received IEEE SSCS Student Travel Grant Award in 2017, ASSCC.

     

  • A 33-GHz LNA for 5G Wireless Systems in 28-nm Bulk CMOS

    A 33-GHz LNA for 5G Wireless Systems in 28-nm Bulk CMOS

    Abstract: This talk presents a design procedure of a compact 33-GHz low noise amplifier (LNA) for 5G applications realized in 28-nm LP CMOS. Based on the unique set of challenges presented by advanced nanoscale CMOS, the emphasis is put here on the optimization of design and layout techniques for active and passive components in the presence of rigorous metal density rules and other back-end-of-the-line (BEOL) challenges. All passive components are designed and optimized with full-wave electromagnetic simulations for a high quality factor. In addition, layout techniques help to miniaturize the total area as the suggested 5G frequency band of 33 GHz is not high enough to provide a sufficiently compact chip size. The resulting increase in the concentration of required metal fills furthermore makes this optimization more challenging. The fabricated LNA consists of two cascode stages with a total core area of 0.68×0.34 mm2. It exhibits 4.9dB noise figure and 18.6 dB gain at 33 GHz while consuming only 9.7mW from a 1.2V power supply.

    Bio: Mahsa Keshavarz Hedayati received her BSc and MSc degree in Electrical Engineering from Amirkabir University of Technology, Tehran, Iran in 2008 and 2011, respectively. In September 2012 she started her PhD in Amirkabir University of Technology. In September 2015 she then joined the Analog, RF and Mixed-signal research group in University College Dublin supervised by Prof. Bogdan Staszewski as a visiting PhD student. Since September 2017 she has been working for Decawave as an RFIC design engineer.

  • A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path

    A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path

     

    Bio: Yizhe Hu was born in Chenzhou, Hunan, China. He received the B.Sc. degree (summa cum laude) in microelectronics from Harbin Institute of Technology (HIT), Harbin, China, in 2013, and the PhD degree in microelectronics from University College Dublin (UCD), Dublin, Ireland, in 2019. He is currently working as a postdoctoral researcher with Prof. R. Bogdan Staszewski in UCD. From 2013 to 2014, he was with Fudan University, Shanghai, China, where he was involved in RFIC design as a postgraduate researcher. From May 2016 to Oct 2017, he was consulting for the PLL Group of HiSilicon, Huawei Technologies, China, designing 16nm DCOs and ADPLLs. Since June 2018, he has been consulting for the Mixed-Signal Design Department, TSMC, for a new type of PLL design. His research interests include RF/mm-wave integrated circuits and systems for wireless communications. Dr. Hu has served as a frequent reviewer for the IEEE JSSC, TCAS-I/II, and TMTT.

  • A 0.2-V 30-MS/s 11b-ENOB Open-Loop VCO-Based ADC in 28-nm CMOS

    A 0.2-V 30-MS/s 11b-ENOB Open-Loop VCO-Based ADC in 28-nm CMOS

    Abstract: We present a 0.2-V open-loop voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) intended for IoT wireless sensor nodes. A resistor-based frequency-tuning scheme helps in mitigating odd-order harmonic distortion induced by the VCO nonlinear transfer characteristic. It also provides a reconfigurable input range, allowing it to exceed the supply by 2.5× (single-ended), and maintaining tolerance against ±10% supply variations. Latch, flip-flops, and logic gates within the frequency-to-digital converter are designed for minimum propagation delays, allowing sampling at 30 MS/s. The ADC is implemented in 28-nm CMOS and achieves a peak SNDR of 68 dB, equivalent to an ENOB of 11, over a 61-kHz bandwidth with a 1-Vpp input differential sinewave. It consumes 7 μW, resulting in a state-of-the-art Walden and Schreier FoM of 27.8 fJ/c-s and 167.4 dB, respectively.

    Bio: Viet Nguyen received the B.Sc. and M.Sc. degrees in Electronic and Computer Engineering from University College Dublin (UCD), Dublin, Ireland, in 2016 and 2017, respectively. He is currently pursuing the Ph.D. degree in Integrated Circuits at University College Dublin (UCD), Dublin, Ireland. His current research interests lies in time-mode data conversion and signal processing, including ultra-low voltage (ULV) VCO-based ADCs and Time-to-digital converters (TDCs).