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2018

  1. Hu, T. Siriburanon, R. Staszewksi. “A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path”, IEEE Journal of Solid-State Circuits, July 2018 (JSSC)
  2. Mai and M.P. Kennedy. “A Design Method for a Nested MASH-SQ Hybrid Divider Controller for Fractional-N Frequency Synthesizers”, IEEE Trans. Circuits and Systems-Part I, 65(*):***-***, ***. 2018. (TCAS-I)
  3. O’Connell, I, and O’Riordan, (2018) “Techniques for reducing ULP device power consumption”, Industry Session 5: Energy Harvesting, APEC, Mar 2018
  4. Mai and M.P. Kennedy. Observations and Analysis of Wandering Spurs in MASH-Based Fractional-N Frequency Synthesizers. IEEE Trans. Circuits and Systems-Part II, **(*):***-***, May 2018. (TCAS-II)
  5. M. Salgado, A. Dicataldo, D. O’Hare, I. O’Connell, J. M. de la Rosa, “Behavioural Modelling of SAR ADCs in Simulink”, IEEE International Symposium on Circuits and Systems, (ISCAS) May 2018
  6. Asghar, S. Afridi, A. Pillai, A. Schuler, J. M. de la Rosa, I. O’Connell, “A 2MS/S, 11.22 ENOB, 3.2 Vpp-D SAR ADC with Improved DNL and Offset Calculation”, IEEE International Symposium on Circuits and Systems, (ISCAS) May 2018
  7. Donnelly, H. Mo and M.P. Kennedy. High-Speed Nested Cascaded MASH Digital Delta-Sigma Modulator-Based Divider Controller. In Proc. ISCAS 2018, pages ***-***, Florence, **-** May 2018.

2017

  1. W. Cao, Y. Li, and A. Zhu, (2017) “Digital Suppression of Transmitter Leakage in FDD RF Transceivers: Aliasing Elimination and Model Selection,” IEEE Transactions on Microwave Theory and Techniques, 65, early access, Dec. 2017
  2. Kelly, N. and Zhu, A. (2017) ‘Direct Error-Searching SPSA Based Model Extraction for Digital Predistortion of RF Power Amplifiers’. IEEE Transactions on Microwave Theory and Techniques, 65
  3. Wang, H., Li, G., Zhou, C., Tao, W., Liu, F., and Zhu, A. (2017) ‘1-bit Observation for Direct-Learning-Based Digital Predistortion of RF Power Amplifiers’. IEEE Transactions on Microwave Theory and Techniques, 65 (07):2465-2475.
  4. Cao, W., and Zhu, A. (2017) ‘A Modified Decomposed Vector Rotation-Based Behavioral Model With Efficient Hardware Implementation for Digital Predistortion of RF Power Amplifiers’. IEEE Transactions on Microwave Theory and Techniques, 65 (07):2443-2452
  5. Cao, W., Li, Y., and Zhu, A. (2017) Magnitude-Selective Affine Function Based Digital Predistorter for RF Power Amplifiers in 5G Small-Cell Transmitters 2017 IEEE MTT-S International Microwave Symposium (IMS) Honolulu, Hawai’i, USA, , 04-JUN-17 – 09-JUN-17
  6. Hu, T. Siriburanon, R. Staszewski, “A 30-GHz Class-F23 Oscillator in 28nm CMOS Using Harmonic Extraction and Achieving 120 kHz 1⁄f 3 Corner” ESSCIRC Sept 2017
  7. Mo and M.P. Kennedy. “Masked Dithering of MASH Digital Delta-Sigma Modulators with Constant Inputs using Multiple Linear Feedback Shift Registers”, IEEE Trans. Circuits and Systems-Part I (TCAS-I), June 2017
  8. W. Kuo, N. Pourmousavian, T. Siriburanon, R. Staszewski, ”A 0.5V 1.6mW 2.4GHz Fractional-N All-Digital PLL for Bluetooth LE with PVT-Insensitive TDC using Switched-Capacitor Doubler in 28nm CMOS,” IEEE Symposium on VLSI Circuits, June 2017
  9. Facchin; S. Zhou; M. Power; A. Jain; C. Scarcella; C. Antony; P. Townsend; P. Ossieur, “A 20Gbaud/s PAM-4 65nm CMOS optical receiver using 3D solenoid based bandwidth enhancement”, IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017
  10. Zhou, H. Wu, K. Sadeghipour, C. Scarcella, C. Eason, M. Rensing, M. Power, C. Antony, P. O’Brien, P. Townsend and P. Ossieur, “Optimization of PAM-4 transmitters based on Lumped Silicon Photonic MZMs for High-Speed Short-reach Optical Links”, Optics Express, vol. 25, issue: 4, pp. 4312-4325, Feb 2017
  11. Mo and M.P. Kennedy. “Influence of Initial Conditions on the Fundamental Periods of LFSR-Dithered MASH Digital Delta-Sigma Modulators with Constant Inputs”. IEEE Trans. Circuits and Systems-Part II, 64(4):372-376, (TCAS-II) Apr 2017.
  12. P. Kennedy, H. Mo and D. Mai. “Nonlinearity-Induced Spurious Tones and Noise in Fractional-N Frequency Synthesizers”, In Proc. URSI Symposium 2017, pages ***-***, Dublin, 8-9 March 2017.
  13. P. Kennedy, H. Mo and D. Mai. “Nonlinearity-Induced Spurious Tones and Noise in Digitally-Assisted Frequency Synthesizers”, In Proc. ISCAS 2017, pages ***-***, Baltimore, **-** May 2017.
  14. Galeone and M.P. Kennedy. “Comparison of Simulation Strategies for Estimating Phase Noise in Oscillators”, In Proc. PRIME 2017, pages ***-***, Taormina, **-** June 2017.
  15. Donnelly and M.P. Kennedy. “Phase Noise in Fractional-N Frequency Synthesizers Employing Successive Requantizers and MASH-SQ Hybrids”, In Proc. PRIME 2017, pages ***-***, Taormina, **-** June 2017.
  16. Mai, H. Mo and M.P. Kennedy. “Observations of the Differences between Closed-loop Behavior and Feed-forward Model Simulations of Fractional-N Frequency Synthesizers”, In Proc. ISSC 2017, pages ***-***, Tralee, **-** June 2017.
  17. Tulisi and M.P. Kennedy. “Performance Limits for Open-Loop Fractional Dividers”, In Proc. ISSC 2017, pages ***-***, Tralee, **-** June 2017.
  18. Kelly, N., Cao, W., and Zhu, A. (2017) ‘Preparing Linearity and Efficiency for 5G: Digital Predistortion for Dual-Band Doherty Power Amplifiers with Mixed-Mode Carrier Aggregation’. IEEE Microwave Magazine, 18 (1):76-84.
  19. Yu, C., Hou, D., Sun, H., Meng, F., Zhu, X.-W., Zhai, J., Chen, J., and Zhu, A. (2017) A Reconfigurable In-Band Digital Predistortion Technique for mm-Wave Power Amplifiers Excited by a Signal with 640 MHz Modulation Bandwidth The 47th European Microwave Conference (EuMC) Nuremberg, Germany, , 08-OCT-17 – 13-OCT-17
  20. McGrath, K., and Zhu, A. (2017) A 2.0-2.5 GHz Frequency-Selectable Oscillator for Digital Predistortion Model Identification of RF Power Amplifiers The International Workshop on Integrated Nonlinear Microwave and Millimetre-wave Circuits (INMMiC) Graz, Austria, , 20-APR-17 – 21-APR-17
  21. Wang, H., Li, G., Zhang, Y., Liu, F. and Zhu, A. (2017) Forward Modeling Assisted 1-Bit Data Acquisition Based Model Extraction for Digital Predistortion of RF Power Amplifiers IEEE Topical Conference on RF/microwave Power Amplifiers for Wireless and Radio Applications (PAWR) Phoenix, AZ, USA, , 16-JAN-17 – 18-JAN-17
  22. Guo, Y. and Zhu, A. (2017) Power Adaptive Decomposed Vector Rotation Based Digital Predistortion for RF Power Amplifiers in Dynamic Power Transmission IEEE Topical Conference on RF/microwave Power Amplifiers for Wireless and Radio Applications (PAWR) Phoenix, AZ, USA, , 16-JAN-17 – 18-JAN-17

2016

  1. Mo and M.P. Kennedy. “Masked Dithering of MASH Digital Delta-Sigma Modulators with Constant Inputs using Linear Feedback Shift Registers”, IEEE Transactions on Circuits and Systems I (TCAS-I), 2016
  2. Xia, J., Yang, M., Guo, Y., and Zhu, A. (2016) ‘A Broadband High-Efficiency Doherty Power Amplifier with Integrated Compensating Reactance’. IEEE Transactions on Microwave Theory and Techniques, 64 (07):2014-2024.
  3. Yang, M., Xia, J., Guo, Y., and Zhu, A. (2016) ‘Highly Efficient Broadband Continuous Inverse Class-F Power Amplifier Design Using Modified Elliptic Low-Pass Filtering Matching Network’. IEEE Transactions on Microwave Theory and Techniques, 64 (05):1515-1525.
  4. Kelly, N., and Zhu, A. (2016) ‘Low Complexity Stochastic Optimization-Based Model Extraction for Digital Predistortion of RF Power Amplifiers’. IEEE Transactions on Microwave Theory and Techniques, 64 (05):1373-1382.
  5. Yu, C., Sun, H., Zhu, X., Hong, W., and Zhu, A. (2016) A Channelized Sideband Distortion Model for Suppressing Unwanted Emission of Q-band Millimeter Wave Transmitters 2016 IEEE MTT-S International Microwave Symposium (IMS) San Francisco, CA, USA, , 22-MAY-16 – 27-MAY-16
  6. Xia, J., Yang, M., and Zhu, A. (2016) ‘Improved Doherty Amplifier Design with Minimum Phase Delay in Output Matching Network for Wideband Application’. IEEE Microwave and Wireless Components Letters, 26 (11):915-917.
  7. Liu, S., Lv, N., Ma, H., and Zhu, A. (2016) ‘Adaptive semiblind background calibration of timing mismatches in a two-channel time-interleaved analog-to-digital converter’. Analog Integrated Circuits and Signal Processing, online access .
  8. Huang, G., Yu, C., and Zhu, A. (2016) ‘Analog Assisted Multichannel Digital Post-Correction for Time-Interleaved ADCs’. IEEE Transactions on Circuits and Systems II: Express Briefs, 63 (8):773-777.
  9. Wang, Y., Zhu, A., and Brazil, T. J. (2016) Real-Valued Discrete-Time Impulse Response Representation of Bandpass S-parameters The 46th European Microwave Conference (EuMC) London, UK
  10. Zhu, A. (2016) Behavioral Modeling for Digital Predistortion of RF Power Amplifiers: from Volterra Series to CPWL Functions (invited) IEEE Topical Conference on RF/microwave Power Amplifiers for Wireless and Radio Applications (PAWR)Austin, Texas, USA, , 24-JAN-16 – 27-JAN-16
  11. Mai, H. Mo and M.P. Kennedy. Comments on “Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division.” In Proc. ICECS 2016, pages 1-6, Monaco, 11-14 December 2016 (to appear).
  12. Mo, X. Tan and M.P. Kennedy. Maximizing the Fundamental Period of a Dithered Digital Delta-Sigma Modulator With Constant Input. In Proc. ICECS 2016, pages 1-6, Monaco, 11-14 December 2016 (to appear).
  13. Donnelly and M.P. Kennedy. On the Statistical Properties of Phase Noise in Fractional-N Frequency Synthesizers Using Successive Requantizers. In Proc. ICECS 2016, pages 1-6, Monaco, 11-14 December 2016 (to appear).
  14. Marnane, V. Marotta and M.P. Kennedy. Yet Another Spur Mechanism in a Charge-Pump Based Fractional-N PLL. In Proc. ICECS 2016, pages 1-6, Monaco, 11-14 December 2016 (to appear).
  15. Huang G. et al. Analog Assisted Multichannel Digital Postcorrection for Time-Interleaved ADCs. IEEE Trans. Circuits and Systems-Part II, 2016 (in press).
  16. P. Kennedy, H. Mo, Z. Huang and J.P. Lana. A Method to Quantify the Dependence of Spur Heights on Offset Current in a CP-PLL. In Proc. ISCAS 2016, Montreal, 22-25 May 2016.
  17. Marotta, G. Macera, M.P. Kennedy and E. Napoli. Comparative Analysis of Differential Colpitts and Cross-Coupled VCOs in 180nm Si-Ge HBT. In Proc. ISCAS 2016, Montreal, 22-25 May 2016.
  18. Mo, G. Hu and M.P. Kennedy. Comparison of analytical predictions of the noise floor due to static charge pump mismatch in fractional-N frequency synthesizers. In Proc. ISCAS 2016, Montreal, 22-25 May 2016.
  19. Macera, V. Marotta, M.P. Kennedy and E. Napoli. A Back-To-Back Series Varactor Configuration Minimizing the Amplitude-to-Phase Noise Conversion in Si-Ge HBT Technology VCOs. In Proc. ISSC 2016, pages 1-6, Derry, 21-22 June 2016.
  20. Mai, H. Mo and M.P. Kennedy. Comparison of the Simulated Performance of Two Successive Requantizers in a Fractional-N Frequency Synthesizer with a Piecewise-Linear Charge-Pump. In Proc. ISSC 2016, pages 1-6, Derry, 21-22 June 2016.
  21. Macera, V. Marotta, M.P. Kennedy and E. Napoli. The Low Power and Wide Tuning Range Advantages of Armstrong VCOs in 180 nm Si-Ge HBT Technology. In Proc. ISSC 2016, pages 1-6, Derry, 21-22 June 2016.
  22. Mo and M.P. Kennedy. Influence of Initial Conditions on the Fundamental Periods of LFSR-Dithered MASH Digital Delta-Sigma Modulators with Constant Inputs. IEEE Trans. Circuits and Systems-Part II, 2016 (in press).
  23. Iordanov P. et al, “Computation of the Real Structured Singular Value via Pole Migration”, Journal of Robust and Nonlinear Control, 2016.

2015

  1. Mooney J. et al, “Dithered Multi-Bit Sigma-Delta Modulator Based DPWM for DC-DC Converters”, IEEE Applied Power Electronics Conference APEC 2015
  2. Halton M. et al, “Robust Analysis and Synthesis Design Tools for Digitally Controlled Power Converters”, IEEE Applied Power Electronics Conference APEC 2015
  3. Pepe D. et al, “A 78.8-92.8 GHz 4-bit 0-360º Active Phase Shifter in 28nm FDSOI CMOS with 2.3 dB Average Peak Gain”, Accepted for publication at IEEE European Solid State Circuits Conference (ESSCIRC), 2015
  4. Sadeghipour et al, “Design of a Sample-and-Hold Analog Front End for a 56Gb/s PAM-4 Receiver Using 65nm CMOS”, International Symposium on Circuits and Systems (ISCAS) 2015
  5. Iordanov P. et al, “Computation of the Real Structured Singular Value via Pole Migration”, Journal of Robust and Nonlinear Control, 2015
  6. Zhu A. et al, “Simplified Volterra Series Based Background Calibration for High Speed High Resolution Pipelined ADCs”, IEEE MWSCAS 2015

2014

  1. Effler S., et al, “Scalable Digital Power Controller with Phase Alignment and Frequency Synchronization”, IEEE Transactions on Circuits and Systems I (TCAS-I), 2014
  2. Ossieur P., et al, “A 1V 2mW 17GHz Multi-Modulus Frequency Divider Based on TSPC Logic Using 65nm CMOS”, IEEE European Solid State Circuits Conference (ESSCIRC), 2014
  3. Kennedy M., et al., “0.3-4.3 GHz Frequency-Accurate Fractional-N Frequency Synthesizer with Integrated VCO and Nested Mixed-Radix Digital Delta-Sigma Modulator-Based Divider Controller”, IEEE Journal of Solid State Circuits (JSSC), May 2014
  4. Brandonisio F., et al, “Noise-Shaping All-Digital Phase-Locked Loops: Modeling, Simulation, Analysis and Design”, Springer Book, 2014
  5. Pepe D. et al, “32 dB Gain W-band LNA in 28 nm Bulk CMOS”, ICECS 2014
  6. Pepe D. et al, “32 dB Gain W-band LNA in 28 nm Bulk CMOS”, IEEE Microwave and Wireless Component Letters, 2014
  7. A. Quadir, et al, “An inductorless linear optical receiver for 20Gbaud/s (40Gb/s) PAM-4 modulation using 28nm CMOS”, International Symposium on Circuits and Systems (ISCAS’2014), Melbourne, Australia, June 2014

2013

  1. Ossieur P., et al, “A 10Gb/s Linear Burst-Mode Receiver in 0.25um SiGe:C BiCMOS”, IEEE Journal of Solid State Circuits (JSSC), Feb 2013
  2. Mooney J., et al, “Application-Specific Instruction-Set Processor for Control of Multi-Rail DC-DC Converter Systems”, IEEE Transactions on Circuits and Systems I (TCAS-I), January 2013
  3. Kennedy M., et al., “High Speed, High Accuracy Fractional-N Frequency Synthesizer using Nested Mixed-Radix Digital Sigma-Delta Modulators”, IEEE European Solid State Circuits Conference (ESSCIRC), Sep 2013
  4. Kennedy M. et al, “A high frequency ‘‘divide-by-odd number’’ CMOS LC injection-locked frequency divider”, journal of Analog Integrated Circuits and Signal Processing, Springer, October 2013.
  5. Merini L. et al, “Analyses and Design of 95-GHz SoC CMOS Radiometers for Passive Body Imaging”, accepted for publication in the journal of Analog Integrated Circuits and Signal Processing, Springer.
  6. Wang N. et al, “3-D Power Supply in Package enabled by high frequency, silicon-based, micro-magnetic Inductors”, in proceedings of IEEE Electronic Components and Technology Conference (ECTC),

2012

  1. Scharrer M., et al, “Efficient Bi-directional Digital Communication Scheme for Isolated Switch Mode Power Converters”, IEEE Transactions on Circuits and Systems I (TCAS-I), December 2012
  2. Quadir N., et al, “A 56Gb/s PAM-4 VCSEL driver circuit”, Irish Systems and Signals Conference (ISSC), June 2012.
  3. Iordanov P., et al, “Discrete-time Modelling and Robust Analysis of a Buck Converter”, in Proceedings of the 7th IFAC Symposium on Robust Control Design (ROCOND), June 2012.
  4. Keady A., et al, “12 MHz to 5800 MHz Fully Integrated, Dual Path Tuned, Low Jitter, LC-PLL Frequency Synthesizer,” in Proceedings of IET Irish Signals and Systems Conference (ISSC), 2012
  5. Mereni L., et al, “Feasibility Study Including Detector Non-Idealities of a 95-GHz CMOS SoC Radiometer for Passive Imaging”, in proceedings of IEEE International Conference on Electronics, Circuits, and Systems (ICECS),
  6. Merini L., et al, “Feasibility and Challenges of a 95-GHz SoC Radiometer for W-Band Passive Imaging, ” in Proceedings of IET Irish Signals and Systems Conference (ISSC), 2012
  7. Awan M., et al, “A “Divide-by-Odd Number” Direct Injection CMOS LC Injection-Locked Frequency Divider”, in proceedings of IEEE International Conference on Electronics, Circuits, and Systems (ICECS),
  8. Mullane B., et al, “A 100dB SFDR 0.5V pk-pk band-pass DAC implemented on a Low Voltage CMOS Process,”Book Chapter, VLSI-SoC: The Advanced Research for Systems on Chip, VLSI-SoC 2011 Revised Selected Papers, 2012

2011

  1. Mullane B., et al, A high performance band-pass DAC architecture and design targeting a low voltage silicon process, in Proceedings of IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2011
  2. O’Brien V., et al, “High order mismatch noise shaping for bandpass DACs,” in Proceedings of IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2011.
  3. Collins D., et al, “Fast Digital Calibration of Static Phase Offset in Charge-Pump Phase-Locked Loops”, in Proceedings of IET Irish Signals and Systems Conference (ISSC), 2011

2010

  1. Hannon J., et al, “Design of a DC-DC Converter with Co-Packaged Inductor”, in Proceedings of IEEE International Workshop on Power Supply On Chip, (PowerSoC), 2010