PUBLICATIONS

Titlecol-2 HiddenAuthorscol-4 hiddencol-5 hiddenConference / Journalxcol-7 hiddenYearDOI
Wandering Spurs in MASH 1-1 Delta-Sigma Modulators Y. Donnelly, M. P. KennedyTCAS-1201910.1109/TCSI.2019.2893435
Wandering Spurs in MASH 1-1 Delta-Sigma ModulatorsY. Donnelly, M. P. Kennedy, TCAS-I, 201910.1109/TCSI.2019.2893435
Unbalanced power amplifier: An architecture for broadband back-off efficiency enhancementG. Nikandish, R. B. Staszewski and A. Zhu, JSSC202110.1109/JSSC.2020.3014244
Ultra-Wideband Dual-Mode Doherty Power Amplifier Using Reciprocal Gate Bias for 5G Applications Li M, Pang J, Li Y, Zhu AMTT202010.1109/TMTT.2019.2932977
Time-skew estimation for random sampling sequence time-interleaved ADCsA. Salib, B. Cardiff, M. F. FlanaganTCAS-II, 202010.1109/TCSII.2019.2956101
Time-Skew Estimation for Random Sampling Sequence Time-Interleaved ADCs A. Salib, B. Cardiff, M. F. FlanaganTCAS-II202010.1109/TCSII.2019.2956101
Techniques for reducing ULP device power consumptionO’Connell, I, and O’Riordan, APEC2018
Scalable Digital Power Controller with Phase Alignment and Frequency Synchronization Effler S., et alTCAS-I201410.1109/TCSI.2013.2283694
Robust Analysis and Synthesis Design Tools for Digitally Controlled Power Converters”Halton M. et alAPEC201510.1109/APEC.2015.7104369
Recent Advances and Trends in Noise Shaping SAR ADCsG.M. Salgado, D. O’Hare, I. O’ConnellTCAS-II202010.1109/TCSII.2020.3046170
Quantum Computer on a Chip," Workshop (1-hr), WSD-8, "Cryogenic Electronics for Quantum Computing and Beyond: Applications, Devices, and CircuitsR. B. Staszewskitest2021
Prediction of Phase Noise and Spurs in a Nonlinear Fractional-N Frequency SynthesizerY. Donnelly; M. P. KennedyTCAS-I201910.1109/TCSI.2019.2925181
Position-based CMOS charge qubits for scalable quantum processors at 4KR. B. Staszewski, P. Giounanlis, A. Esmailiyan, H. Wang, I. Bashir, C. Cetintepe, D. Andrade-Miceli, M. Asker, D. Leipold, T. Siriburanon, A. Sokolov and E. BlokhinaISCAS202010.1109/ISCAS45731.2020.9180789
Planar High Frequency Magnetic Material Large Signal Measurement and Performance Factor Comparisons for Planar Toroidal Inductors Embedded in PCB R. Murphy et al, APEC, 2021
Passive SC ?? modulator based on pipelined charge-sharing rotation in 28-nm CMOSH. Wang, F. Schembari, and R. B. StaszewskiTCAS-I201910.1109/TCSI.2019.2944467
Passive SC ?? Modulator Based on Pipelined Charge-Sharing Rotation in 28-nm CMOSH. Wang, F. Schembari, and R. B. StaszewskiTCAS-I201910.1109/TCSI.2019.2944467
Oscillator flicker phase noise: A tutorialY. Hu, T. Siriburanon and R. B. StaszewskiTCAS-II, 202110.1109/TCSII.2020.3043165
Observations and Analysis of Wandering Spurs in MASH-Based Fractional-N Frequency SynthesizersD. Mai, H. Mo, M.P. KennedyTCAS-II201810.1109/TCSII.2018.2821636
Nonlinearity-induced spurious tones and noise in digitally-assisted frequency synthesizers M.P. Kennedy, H. Mo and D. MaiISCAS201710.1109/ISCAS.2017.8050553
Modeling and Analysis of Error Feedback Noise-Shaping SAR ADCs7. G. M. Salgado, D. O'Hare, and I. O'ConnellISCAS202010.1109/ISCAS45731.2020.9180995
Mitigation of “Horn Spurs” in a MASH-Based Fractional-N CP-PLL V. Mazzaro, M. P. KennedyTCAS-II202010.1109/TCSII.2020.2984359
Masked Dithering of MASH Digital Delta-Sigma Modulators with Constant Inputs using Multiple Linear Feedback Shift RegistersH. Mo and M.P. KennedyTCAS-I201710.1109/TCSI.2017.2670365
Masked Dithering of MASH Digital Delta-Sigma Modulators with Constant Inputs using Linear Feedback Shift RegistersH. Mo and M.P. KennedyTCAS-I, 201610.1109/TCSI.2017.2670365
MASH-Based Divider Controllers for Mitigation of Wandering Spurs in a Fractional-N Frequency SynthesizerD. Mai, M. P. KennedyTCAS-I, 202110.1109/TCSI.2020.3035538
Magnitude-Selective Affine Function Based Digital Predistorter for RF Power Amplifiers in 5G Small-Cell Transmitters33. Cao, W., Li, Y., and Zhu, AMTT201710.1109/MWSYM.2017.8058921
Low Complexity Stochastic Optimization-Based Model Extraction for Digital Predistortion of RF Power AmplifiersKelly, N., and Zhu, A. MTT201610.1109/TMTT.2016.2547383
Linearization Angle Widened Digital Predistortion for 5G MIMO Beamforming TransmittersQ. Luo, …X. Wang, C. Chu, A. Zhu MTT2021
Jitter Minimization in Digital PLLs with Mid-Rise TDCsL. Avallone, M. P. Kennedy, S. Karman, C. Samori, S. LevantinoTCAS-I202010.1109/TCSI.2019.2959252
Intuitive understanding of flicker noise reduction via narrowing of conduction angle in voltage-biased oscillators Y. Hu, T. Siriburanon, and R. B. Staszewski, TCAS-II, 201910.1109/TCSII.2019.2896483
Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased OscillatorsY. Hu; T. Siriburanon; R. B. StaszewskiTCAS-II201910.1109/TCSII.2019.2896483
Intuitive understanding of flicker noise reduction via narrowing of conduction angle in voltage-biased oscillators Y. Hu, T. Siriburanon, and R. B. StaszewskiTCAS-II201910.1109/TCSII.2019.2896483
Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased OscillatorsY. Hu; T. Siriburanon; R. B. StaszewskiTCAS-II201910.1109/TCSII.2019.2896483
Instantaneous Sample Indexed Magnitude-Selective Affine Function-Based Behavioral Model for Digital Predistortion of RF Power Amplifiers
Y. Li ; W. Cao ; A. Zhu, (MTT), 201810.1109/TMTT.2018.2855134
Influence of Initial Conditions on the Fundamental Periods of LFSR-Dithered MASH Digital Delta-Sigma Modulators with Constant InputsH. Mo and M.P. Kennedy. TCAS-II,201710.1109/TCSII.2016.2567480
Influence of Initial Conditions on the Fundamental Periods of LFSR-Dithered MASH Digital Delta-Sigma Modulators with Constant InputsH. Mo and M.P. KennedyTCAS-II201610.1109/TCSII.2016.2567480
Influence of Initial Condition on Wandering Spur Pattern in a MASH-Based Fractional-N Frequency SynthesizerD. Mai, M. P. KennedyTCAS-II202010.1109/TCSII.2020.2985640
Highly Efficient Broadband Continuous Inverse Class-F Power Amplifier Design Using Modified Elliptic Low-Pass Filtering Matching NetworkYang, M., Xia, J., Guo, Y., and Zhu, AMTT201610.1109/TMTT.2016.2544318
High-Speed Nested Cascaded MASH Digital Delta-Sigma Modulator-Based Divider Controller.Y. Donnelly, H. Mo and M.P. KennedyISCAS201810.1109/ISCAS.2018.8351624
High Speed, High Accuracy Fractional-N Frequency Synthesizer using Nested Mixed-Radix Digital Sigma-Delta ModulatorsKennedy M., et al., ESSCIRC201310.1109/ESSCIRC.2013.6649118
High Order Mismatch Shaping for Low Oversampling RatesV. O’Brien; B. MullaneTCAS-II201910.1109/TCSII.2019.2904180
High Order Mismatch Shaping for Low Oversampling RatesV. O’Brien; B. MullaneTCAS-II201910.1109/TCSII.2019.2904180
Electrostatic control and entanglement of CMOS position-based qubits P. Giounanlis, A. Sokolov, E. Blokhina, I. Bashir, D. Leipold and R. B. StaszewskiISCAS,202010.1109/ISCAS45731.2020.9180721
Efficient Bi-directional Digital Communication Scheme for Isolated Switch Mode Power ConvertersScharrer M., et alTCAS-1201210.1109/TCSI.2012.2206450
Dithered Multi-Bit Sigma-Delta Modulator Based DPWM for DC-DC ConvertersMooney J. et al, APEC201510.1109/APEC.2015.7104752
Direct Error-Searching SPSA Based Model Extraction for Digital Predistortion of RF Power Amplifiers'30. Kelly, N. and Zhu, A. MTT201710.1109/TMTT.2017.2748128
Digital Suppression of Transmitter Leakage in FDD RF Transceivers: Aliasing Elimination and Model Selection29. W. Cao, Y. Li, and A. Zhu, MTT201710.1109/TMTT.2017.2772789
Design of Ultra-Low-Power Discrete-time Receivers for the Internet of ThingsS. Binsfeld-Ferreira and R. B. StaszewskiISCAS2020
Design of a Sample-and-Hold Analog Front End for a 56Gb/s PAM-4 Receiver Using 65nm CMOSK. Sadeghipour et alICAS201510.1109/ISCAS.2015.7168956
Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas Rejection. K-F. Un, F. Zhang, P-I. Mak, R. P. Martins, A. Zhu, R. Bogdan StaszewskiTCAS-II201910.1109/TCSII.2019.2903561
Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas RejectionK-F. Un, F. Zhang, P-I. Mak, R. P. Martins, A. Zhu, R. Bogdan StaszewskiTCAS-II201910.1109/TCSII.2019.2903561
Continuous User Authentication via the ECG Using IoT Wearable Devices C. Smyth, G. Wang, A. Nag, B. Cardiff, D. John ISCAS, 202110.1109/ISCAS51556.2021.9401741
Comparison of analytical predictions of the noise floor due to static charge pump mismatch in fractional-N frequency synthesizers H. Mo, G. Hu and M.P. KennedyISCAS201610.1109/ISCAS.2016.7539077
Comparative analysis of differential colpitts and cross-coupled VCOs in 180 nm Si-Ge HBT technologyV. Marotta, G. Macera, M.P. Kennedy and E. NapoliISCAS201610.1109/ISCAS.2016.7538883
Broadband Fully Integrated GaN Power Amplifier With Minimum-Inductance BPF Matching and Two-Transistor AM-PM Compensation G. Nikandish, R. B. Staszewski and A. ZhuTCAS-I202010.1109/TCSI.2020.3002395
Broadband fully integrated GaN power amplifier with embedded minimum inductor bandpass filter and AM-PM compensationG. Nikandish, R. B. Staszewski, and A. ZhuESSCIRC201910.1109/LSSC.2019.2927855
Behavioral Modeling of SAR ADCs in Simulink26. S. Asghar, S. Afridi, A. Pillai, A. Schuler, J. M. de la Rosa, I. O’Connell, (ISCAS) 201810.1109/ISCAS.2018.8351056
Application-Specific Instruction-Set Processor for Control of Multi-Rail DC-DC Converter SystemsMooney J., et alTCAS-1201310.1109/TCSI.2012.2215783
Analysis of Wandering Spur Patterns in a Fractional-N Frequency Synthesizer with a MASH-Based Divider Controller
 D. Mai, M. P. KennedyTCAS-I202010.1109/TCSI.2019.2958781
Analog Assisted Multichannel Digital Postcorrection for Time-Interleaved ADCsHuang, G., Yu, C., and Zhu, ATCAS-II .201610.1109/TCSII.2016.2530899
Analog Assisted Multichannel Digital Postcorrection for Time-Interleaved ADCsHuang, G., Yu, C., and Zhu, ATCAS-II, 201610.1109/TCSII.2016.2530899
An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ?? Loop,P. Chen, X. Huang, Y. Chen, L. Wu, R. Staszewski. TCAS-I201810.1109/TCSI.2018.2857999
An inductorless linear optical receiver for 20Gbaud/s (40Gb/s) PAM-4 modulation using 28nm CMOS N.A. Quadir, et alISCAS201410.1109/ISCAS.2014.6865674
An event-driven quasi-level-crossing delta modulator based on residue quantizationH. Wang, F. Schembari, and R. B. StaszewskiJSSC202010.1109/JSSC.2019.2950175
An Adaptive-Resolution Quasi-Level-Crossing-Sampling ADC Based on Residue Quantization in 28-nm CMOSH. Wang, F. Schembari, M. Mi?kowicz, R.B. Staszewskitest201910.1109/LSSC.2019.2899723
An Adaptive-Resolution Quasi-Level-Crossing Delta Modulator With VCO-Based Residue Quantizer H. Wang, V. Nguyen, F. Schembari, and R. B. StaszewskiTCAS-II202010.1109/TCSII.2020.2979078
An adaptive-resolution quasi-level-crossing Delta modulator with VCO-based residue quantizerH. Wang, V. Nguyen, F. Schembari, and R. B. StaszewskiTCAS-II202010.1109/TCSII.2020.2979078
An Active-under-Coil RFDAC with Analog Linear Interpolation in 28-nm CMOSF. Zhang, P. Chen, J. S. Walling, A. Zhu, R.B. StaszewskiTCAS-I202110.1109/TCSI.2021.3059368
A Type-II Phase-Tracking ReceiverS. Hu, J. Du, P. Chen, H. M. Nguyen, P. Quinlan, B. StaszewskiJSSC202010.1109/JSSC.2020.3005797
A Type-II Phase-Tracking Receiver S. Hu, J. Du, P. Chen, H. M. Nguyen, P. Quinlan and R. B. StaszewskiJSSC202110.1109/JSSC.2020.3005797
A tiny complementary oscillator with noise reduction using a triple-8-shaped transformerX. Chen, Y. Hu, T. Siriburanon, J. Du, R. B. Staszewski, and A. ZhuSSC-L, 202010.1109/LSSC.2020.3009205
A method to quantify the dependence of spur heights on offset current in a CP-PLLM.P. Kennedy, H. Mo, Z. Huang and J.P. Lana. ISCAS201610.1109/ISCAS.2016.7538885
A Low-Power 1-V Supply Dynamic ComparatorChevella, S, O’Hare, D and O’Connell, SSC-L202010.1109/LSSC.2020.3009437
A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path Y. Hu, T. Siriburanon, R. StaszewskiJSSC)201810.1109/JSSC.2018.2818681
A low-complexity correlation-based time skew estimation technique for time-interleaved SAR ADCsA. Salib, B. Cardiff, M. F. FlanaganISCAS201710.1109/ISCAS.2017.8050309
A Ka-Band Switched-Capacitor RFDAC Using Edge-Combining in 22nm FD-SOI”H. M. Nguyen, J. S. Walling, A. Zhu, R. B. Staszewski test202110.23919/VLSICircuits52068.2021.9492451
A High-Precision Time Skew Estimation and Correction Technique for Time-Interleaved ADCsY. Donnelly; M. P. KennedyTCAS-I, 201910.1109/TCSI.2019.2925181
A High-Precision Time Skew Estimation and Correction Technique for Time-Interleaved ADCs A. Salib; M. F. Flanagan; B. Cardiff, TCAS-I201910.1109/TCSI.2019.2915282
A Generic Foreground Calibration Algorithm for ADCs with Nonlinear Impairments”28. A. Salib; M. F. Flanagan; B. CardiffISCAS201810.1109/ISCAS.2018.8351187
A Generic Foreground Calibration Algorithm for ADCs with Nonlinear ImpairmentsA. Salib; M. F. Flanagan; B. Cardiff, TCAS-I201910.1109/TCSI.2018.2870529
A Generic Foreground Calibration Algorithm For ADCs with Nonlinear ImpairmentsA. Salib; M. F. Flanagan; B. CardiffTCAS-I, 201910.1109/ISCAS.2018.8351187
A Generalized Signal Quality Estimation Method for IoT SensorsA. John, B. Cardiff, D. JohnISCAS202010.1109/ISCAS45731.2020.9180546
A fully integrated GaN dual-channel power amplifier with crosstalk suppression for 5G massive MIMO transmitters G. Nikandish, R. B. Staszewski and A. ZhuTCAS-II,202110.1109/TCSII.2020.3008365
A fully integrated DAC for CMOS position-based charge qubits with single-electron detector loopback testing”A. Esmailiyan, H. Wang, M. Asker, E. Koskin, D. Leipold, I. Bashir, K. Xu, A. Koziol, E. Blokhina, and R. B. StaszewskiSSC-L202010.1109/LSSC.2020.3018707
A Feedforward and Feedback Constant-Slope Digital-to-Time Converter in 28nm CMOS Achieving P. Chen, F. Zhang, S. Hu and R. B. StaszewskiVLSI2021
A Design Method for a Nested MASH-SQ Hybrid Divider Controller for Fractional-N Frequency SynthesizersD. Mai and M.P. Kennedy.TCAS-I, 201810.1109/TCSI.2018.2816939
A Design Method for a Nested MASH-SQ Hybrid Divider Controller for Fractional-N Frequency SynthesizersD. Mai and M.P. KennedyTCAS-I201810.1109/TCSI.2018.2816939
A Comparative Study of Level-Crossing Sampling Schemes for Event-Driven Electrocardiogram Arrhythmia ClassificationM. Saeed, Q. Wang, O. Märtens, B. Larras, A. Frappé, B. Cardiff, D. John ISCAS, 2021
A Compact 0.2–0.3-V Inverse-Class-F23 Oscillator for Low 1/f3 Noise over Wide Tuning RangeJ. Du, Y. Hu, T. Siriburanon, E. Kobal, P. Quinlan, A. Zhu and R. B. StaszewskiJSSC202110.1109/JSSC.2021.3098770
A clock-phase reuse technique for discrete-time band-pass filtersA. Bozorg and R. B. StaszewskiJSSC202110.1109/JSSC.2021.3086621
A channelized sideband distortion model for suppressing unwanted emission of Q-band millimeter wave transmittersYu, C., Sun, H., Zhu, X., Hong, W., and Zhu, AInternational Microwave Symposium201610.1109/MWSYM.2016.7540308
A Broadband High-Efficiency Doherty Power Amplifier with Integrated Compensating ReactanceXia, J., Yang, M., Guo, Y., and Zhu, AMTT201610.1109/TMTT.2016.2574861
A 78.8-92.8 GHz 4-bit 0-360º Active Phase Shifter in 28nm FDSOI CMOS with 2.3 dB Average Peak GainESSCIRC201510.1109/ESSCIRC.2015.7313829
A 33-GHz LNA for 5G Wireless Systems in 28-nm Bulk CMOSM. Keshavarz Hedayati; A. Abdipour; R. Sarraf Shirazi; C. Cetintepe; R. B. StaszewskiTCAS-II201810.1109/TCSII.2018.2859187
A 31-? W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOSChen P, Zhang F, Zong Z, Hu S, Siriburanon T, Staszewski RBJSSC202010.1109/JSSC.2019.2939663
A 30-GHz Class-F23 Oscillator in 28nm CMOS Using Harmonic Extraction and Achieving 120 kHz 1?f 3 Corner Y. Hu, T. Siriburanon, R. StaszewskiESSCIRC201710.1109/ESSCIRC.2017.8094532
A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB22. J. Du, T. Siriburanon, X. Chen, Y. Hu, V. Govindaraj, A. Zhu and R. B. Staszewski VLSI2021
A 21.7-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency Tracking Loop Achieving 75fs Jitter and -250dB FoM Y. Hu, X. Chen, T. Siriburanon, J. Du, Z. Gao, V. Govindaraj, A. Zhu, R. B. StaszewskiISSCC202010.1109/ISSCC19947.2020.9063024
A 10Gb/s Linear Burst-Mode Receiver in 0.25um SiGe:C BiCMOSJSSC201310.1109/JSSC.2012.2221211
A 2MS/S, 11.22 ENOB, 3.2 Vpp-D SAR ADC with Improved DNL and Offset Calculation”, IEEE International Symposium on Circuits and Systems, S. Asghar, S. Afridi, A. Pillai, A. Schuler, J. M. de la Rosa, I. O’Connell, ISCAS)2018
A 2.0–2.87GHz -249dB FoM 1.1 mW digital PLL exploiting reference-sampling phase detectorJ. Du, T. Siriburanon, Y. Hu, V. Govindaraj, and R. B. StaszewskiSSC-L2020
A 1V 2mW 17GHz Multi-Modulus Frequency Divider Based on TSPC Logic Using 65nm CMOSOssieur P., et alESSCIRC201410.1109/ESSCIRC.2014.6942114
A 1D-CNN Based Deep Learning Technique for Sleep Apnea Detection in Wearable SensorsA. John, B. Cardiff, D. John, ISCAS, 202110.1109/ISCAS51556.2021.9401300
A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation17. K. Xu; F. Kuo; H. R. Chen; L. Cho; C. Jou; M. Chen; R. B. StaszewskiJSSC201910.1109/JSSC.2019.2906803
A 0.36-V 5-MS/s time-mode flash ADC with Dickson-charge-pump-based comparators in 28-nm CMOSA. Esmailiyan, F. Schembari, and R. B. Staszewski, TCAS-I202010.1109/TCSI.2020.2969804
A 0.36-V 5-MS/s time-mode flash ADC with Dickson-charge-pump-based comparators in 28-nm CMOSA. Esmailiyan, F. Schembari, and R. B. StaszewskiTCAS-I202010.1109/TCSI.2020.2969804
A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE with PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOSN. Pourmousavian, F.W. Kuo, T. Siriburanon, M. Babaie, R. StaszewskiJSSC)201910.1109/JSSC.2018.2843337
A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS F. W. Kuo, N. Pourmousavian, T. Siriburanon, R. StaszewskiVLSI201710.1109/JSSC.2018.2843337
A 0.3 V, 35% tuning-range, 60 kHz 1/f3-corner digitally controlled oscillator with vertically integrated switched capacitor banks achieving FoMT of -199 dB in 28-nm CMOSJ. Du, Y. Hu, T. Siriburanon, and R. B. StaszewskiCICC201910.1109/CICC.2019.8780295
A 0.2-V 30-MS/s 11b-ENOB Open-Loop VCO-Based ADC in 28-nm CMOS V. Nguyen, F. Schembari, R. B. Staszewski, SSC-L201910.1109/LSSC.2019.2906777
A 0.02-4.5-GHz LN(T)A in 28-nm CMOS for 5G Exploiting Noise Reduction and Current Reuse”,A. Bozorg, R. B. StaszewskiJSSC202010.1109/JSSC.2020.3018680
A 0.02–4.5 GHz LN(T)A in 28-nm CMOS for 5G exploiting noise reduction and current reuse5. A. Bozorg and R. B. StaszewskiJSSC202110.1109/JSSC.2020.3018680
A 0.01mm2 0.83V Input Range SAR Based Bridge-to-Digital ConverterA. Fordymacka et alSSC-L202010.1109/LSSC.2020.3018427
4.48GHz 0.18?m SiGe BiCMOS Exact-Frequency Fractional-N Frequency Synthesizer with Spurious-Tone Suppression Yielding a -80dBc In-Band Fractional SpurM. P. Kennedy, Y. Donnelly, J. Breslin, S. Tulisi, S. Patil, C. Curtin, S. Brookes, B. Shelly, P. Griffin, M. KeaveneyISSCC201910.1109/ISSCC.2019.8662327
4.48-GHz Fractional- N Frequency Synthesizer With Spurious-Tone Suppression via Probability Mass Redistribution Y. Donnelly, M. P. Kennedy, J. Breslin, S. Tulisi, S. Patil, C. Curtin, S. Brookes, B. Shelly, P. Griffin, M. KeaveneySSC-L201910.1109/LSSC.2019.2943936
1-bit Observation for Direct-Learning-Based Digital Predistortion of RF Power Amplifiers31. Wang, H., Li, G., Zhou, C., Tao, W., Liu, F., and Zhu, A. MTT201710.1109/TMTT.2016.2642945
0.3–4.3 GHz Frequency-Accurate Fractional-N Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital ?-? Modulator-Based Divider Controller Kennedy M., et alJSSC201410.1109/JSSC.2014.2322095
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