Publications

Recent Highlight Publications

  1. Y. Hu, X. Chen, T. Siriburanon, J. Du, Z. Gao, V. Govindaraj, A. Zhu, R. B. Staszewski, “A 21.7-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency Tracking Loop Achieving 75fs Jitter and -250d8 FoM”, (ISSCC), Feb 2020
  2. H. Wang, F. Schembari, and R. B. Staszewski, “An event-driven quasi-level-crossing delta modulator based on residue quantization,” (JSSC), 2019
  3. Chen P, Zhang F, Zong Z, Hu S, Siriburanon T, Staszewski RB, “A 31-μ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS”, (JSSC), Nov 2019
  4. Li M, Pang J, Li Y, Zhu A, “Ultra-Wideband Dual-Mode Doherty Power Amplifier Using Reciprocal Gate Bias for 5G Applications”, (MTT) Oct 2019
  5. G. Nikandish, R. B. Staszewski, and A. Zhu, “Broadband fully integrated GaN power amplifier with embedded minimum inductor bandpass filter and AM-PM compensation,”, (ESSCIRC), Sep 2019
  6. H. Wang, F. Schembari, and R. B. Staszewski, “Passive SC ΔΣ modulator based on pipelined charge-sharing rotation in 28-nm CMOS,” (TCAS-I), Aug. 2019
  7. K. Xu; F. Kuo; H. R. Chen; L. Cho; C. Jou; M. Chen; R. B. Staszewski “A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation”, (JSSC) 2019
  8. A. Salib; M. F. Flanagan; B. Cardiff, “A Generic Foreground Calibration Algorithm for ADCs with Nonlinear Impairments”, Vol 66, Issue 5, (TCAS-I), May 2019
  9. A. Salib; M. F. Flanagan; B. Cardiff, “A High-Precision Time Skew Estimation and Correction Technique for Time-Interleaved ADCs”, (TCAS-I), 2019
  10. Y. Donnelly; M. P. Kennedy “Prediction of Phase Noise and Spurs in a Nonlinear Fractional-N Frequency Synthesizer” (TCAS-I) 2019
  11. J. Du, Y. Hu, T. Siriburanon, and R. B. Staszewski, “A 0.3 V, 35% tuning-range, 60 kHz 1/f3-corner digitally controlled oscillator with vertically integrated switched capacitor banks achieving FoMT of -199 dB in 28-nm CMOS,” (CICC), Apr. 2019
  12. Y. Donnelly, M. P. Kennedy, “Wandering Spurs in MASH 1-1 Delta-Sigma Modulators”, (TCAS-I), 2019
  13. M. P. Kennedy, Y. Donnelly, J. Breslin, S. Tulisi, S. Patil, C. Curtin, S. Brookes, B. Shelly, P. Griffin, M. Keaveney, “4.48GHz 0.18μm SiGe BiCMOS Exact-Frequency Fractional-N Frequency Synthesizer with Spurious-Tone Suppression Yielding a -80dBc In-Band Fractional Spur”, (ISSCC), Feb 2019
  14. P. Chen, X. Huang, Y. Chen, L. Wu, R. Staszewski. “An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ΔΣ Loop”, IEEE Transactions on Circuits and Systems I (TCAS-I) Aug 2018
  15. N. Pourmousavian, F.W. Kuo, T. Siriburanon, M. Babaie, R. Staszewski. “A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE with PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS”, IEEE Journal of Solid-State Circuits, Vol 53 Issue 9, Sep 2018 (JSSC)
  16. Y. Hu, T. Siriburanon, R. Staszewski. “A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path”, IEEE Journal of Solid-State Circuits, July 2018 (JSSC)
  17. D. Mai and M.P. Kennedy. “A Design Method for a Nested MASH-SQ Hybrid Divider Controller for Fractional-N Frequency Synthesizers”, IEEE Trans. Circuits and Systems-Part I, 65(*): April 2018. (TCAS-I)
  18. O’Connell, I, and O’Riordan, (2018) “Techniques for reducing ULP device power consumption”, Industry Session 5: Energy Harvesting, APEC, Mar 2018   
  19. Y. Li ; W. Cao ; A. Zhu, “Instantaneous Sample Indexed Magnitude-Selective Affine Function-Based Behavioral Model for Digital Predistortion of RF Power Amplifiers”, (MTT), 2018
  20. W. Cao, Y. Li, and A. Zhu, (2017) “Digital Suppression of Transmitter Leakage in FDD RF Transceivers: Aliasing Elimination and Model Selection,” IEEE Transactions on Microwave Theory and Techniques, Vol. 65, early access, Dec. 2017 (MTT)
  21. Kelly, N. and Zhu, A. (2017) ‘Direct Error-Searching SPSA Based Model Extraction for Digital Predistortion of RF Power Amplifiers’. IEEE Transactions on Microwave Theory and Techniques, 65 (MTT)
  22. Wang, H., Li, G., Zhou, C., Tao, W., Liu, F., and Zhu, A. (2017) ‘1-bit Observation for Direct-Learning-Based Digital Predistortion of RF Power Amplifiers’. IEEE Transactions on Microwave Theory and Techniques, 65 (07):2465-2475. (MTT)
  23. Cao, W., and Zhu, A. (2017) ‘A Modified Decomposed Vector Rotation-Based Behavioral Model With Efficient Hardware Implementation for Digital Predistortion of RF Power Amplifiers’.  IEEE Transactions on Microwave Theory and Techniques, 65 (07):2443-2452 (MTT)
  24. Cao, W., Li, Y., and Zhu, A. (2017) Magnitude-Selective Affine Function Based Digital Predistorter for RF Power Amplifiers in 5G Small-Cell Transmitters 2017 IEEE MTT-S International Microwave Symposium (IMS) Honolulu, Hawai’i, USA, June 2017
  25. Y. Hu, T. Siriburanon, R. Staszewski, “A 30-GHz Class-F23 Oscillator in 28nm CMOS Using Harmonic Extraction and Achieving 120 kHz 1⁄f 3 Corner”, (ESSCIRC) Sept 2017
  26. H. Mo and M.P. Kennedy. “Masked Dithering of MASH Digital Delta-Sigma Modulators with Constant Inputs using Multiple Linear Feedback Shift Registers”, IEEE Trans. Circuits and Systems-Part I (TCAS-I), June 2017
  27. F. W. Kuo, N. Pourmousavian, T. Siriburanon, R. Staszewski, ”A 0.5V 1.6mW 2.4GHz Fractional-N All-Digital PLL for Bluetooth LE with PVT-Insensitive TDC using Switched-Capacitor Doubler in 28nm CMOS,” IEEE Symposium on VLSI Circuits, June 2017
  28. H. Mo and M.P. Kennedy. “Masked Dithering of MASH Digital Delta-Sigma Modulators with Constant Inputs using Linear Feedback Shift Registers”, IEEE Transactions on Circuits and Systems I (TCAS-I), 2016
  29. Xia, J., Yang, M., Guo, Y., and Zhu, A. (2016) ‘A Broadband High-Efficiency Doherty Power Amplifier with Integrated Compensating Reactance’. IEEE Transactions on Microwave Theory and Techniques, 64 (07):2014-2024. (MTT)
  30. Yang, M., Xia, J., Guo, Y., and Zhu, A. (2016) ‘Highly Efficient Broadband Continuous Inverse Class-F Power Amplifier Design Using Modified Elliptic Low-Pass Filtering Matching Network’. IEEE Transactions on Microwave Theory and Techniques, 64 (05):1515-1525. (MTT)
  31. Kelly, N., and Zhu, A. (2016) ‘Low Complexity Stochastic Optimization-Based Model Extraction for Digital Predistortion of RF Power Amplifiers’. IEEE Transactions on Microwave Theory and Techniques, 64 (05):1373-1382. (MTT)
  32. Yu, C., Sun, H., Zhu, X., Hong, W., and Zhu, A. (2016) A Channelized Sideband Distortion Model for Suppressing Unwanted Emission of Q-band Millimeter Wave Transmitters 2016 IEEE MTT-S International Microwave Symposium (IMS) San Francisco, CA, USA, , 22-MAY-16 – 27-MAY-16
  33. Mooney J. et al, “Dithered Multi-Bit Sigma-Delta Modulator Based DPWM for DC-DC Converters”, IEEE Applied Power Electronics Conference APEC March 2015
  34. Halton M. et al, “Robust Analysis and Synthesis Design Tools for Digitally Controlled Power Converters”, IEEE Applied Power Electronics Conference APEC March 2015
  35. Pepe D. et al, “A 78.8-92.8 GHz 4-bit 0-360º Active Phase Shifter in 28nm FDSOI CMOS with 2.3 dB Average Peak Gain”, Accepted for publication at IEEE European Solid State Circuits Conference (ESSCIRC), 2015
  36. Effler S., et al, “Scalable Digital Power Controller with Phase Alignment and Frequency Synchronization”, IEEE Transactions on Circuits and Systems I (TCAS-I), 2014
  37. Ossieur P., et al, “A 1V 2mW 17GHz Multi-Modulus Frequency Divider Based on TSPC Logic Using 65nm CMOS”, IEEE European Solid State Circuits Conference (ESSCIRC), 2014
  38. Kennedy M., et al., “0.3-4.3 GHz  Frequency-Accurate Fractional-N Frequency Synthesizer with Integrated VCO and Nested Mixed-Radix Digital Delta-Sigma Modulator-Based Divider Controller”, IEEE Journal of Solid State Circuits (JSSC), May 2014
  39. Ossieur P., et al, “A 10Gb/s Linear Burst-Mode Receiver in 0.25um SiGe:C BiCMOS”, IEEE Journal of Solid State Circuits (JSSC), Feb 2013
  40. Mooney J., et al, “Application-Specific Instruction-Set Processor for Control of Multi-Rail DC-DC Converter Systems”, IEEE Transactions on Circuits and Systems I (TCAS-I), January 2013
  41. Kennedy M., et al., “High Speed, High Accuracy Fractional-N Frequency Synthesizer using Nested Mixed-Radix Digital Sigma-Delta Modulators”, IEEE European Solid State Circuits Conference (ESSCIRC), Sep 2013
  42. Scharrer M., et al, “Efficient Bi-directional Digital Communication Scheme for Isolated Switch Mode Power Converters”, IEEE Transactions on Circuits and Systems I (TCAS-I), December 2012

 

Other Publications

  1. A. Salib, B. Cardiff, M. F. Flanagan, “Time-skew estimation for random sampling sequence time-interleaved ADCs”, IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), Jan 2020
  2. K. Pomorski, P. Giounanlis, E. Blokhina, D. Leipold, and R. B. Staszewski, “Analytic view on coupled single-electron lines”, IOP Science – Semiconductor Science and Technology, 2019
  3. P. Giounanlis, E. Blokhina, D. Leipold, and R. B. Staszewski, “A Python-Verilog toolbox for modeling of a Hadamard gate based on position-based CMOS qubits,” (ICECS), Nov. 2019
  4. V. Govindaraj, J. Du, Y. Hu, T. Siriburanon and R. B. Staszewski, “DTC-assisted all-digital phase-locked loop exploiting hybrid time/voltage phase digitization,” (APCCAS), Nov. 2019
  5. Pourmousavian N, Siriburanon T, Feng-Wei Kuo, Babaie M, Staszewski RB, “Clock generation”, chapter in Digitally Enhanced Mixed Signal Systems, pg 255-288
  6. K. Pomorski, P. Giounanlis, E. Blokhina, D. Leipold, and R. Staszewski, “Description of interface between semiconductor and superconducting quantum computer,” XIX National Conference on Superconductivity, Oct. 2019
  7. G. Nikandish, R. B. Staszewski, and A. Zhu, “Breaking bandwidth limit: A review of broadband Doherty power amplifier design for 5G,” IEEE Microwave Magazine, 2019.
  8. G. Nikandish, R. B. Staszewski, and A. Zhu, “A broadband continuous class-F GaN MMIC PA using multi-resonance matching network,” (EuMW) Sept. 2019
  9. G. Nikandish, R. B. Staszewski, and A. Zhu, “Bandwidth enhancement of GaN MMIC Doherty power amplifiers using broadband transformer-based load modulation network,” IEEE Access, 2019
  10. G. Nikandish, R. B. Staszewski, and A. Zhu, “Broadband fully integrated GaN power amplifier with embedded minimum inductor bandpass filter and AM-PM compensation,” (SSC-L), Sept. 2019
  11. K.-F. Un, F. Zhang, P.-I. Mak, R. P. Martins, A. Zhu, and R. B. Staszewski, “Design considerations of the interpolative digital transmitter for quantization noise and replicas rejection”, (TCAS-II), Mar 2019
  12. Z. Gao, Y. Hu, T. Siriburanon, and R. B. Staszewski, “28GHz quadrature frequency generation exploiting injection locked harmonic extractors for 5G communications,” (NEWCAS), June. 2019
  13. E. Koskin, P. Bisiaux, D. Galayko, E. Blokhina, “All-Digital Phase-Locked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping”, (NEWCAS), June 2019
  14. Y. Hu, T. Siriburanon, and R. B. Staszewski, “Intuitive understanding of flicker noise reduction via narrowing of conduction angle in voltage-biased oscillators”, (TCAS-II), 2019
  15. A. Bozorg and R. B. Staszewski, “Two-fold noise-cancelling low-noise amplifier in 28-nm CMOS,” (NEWCAS), Jun. 2019
  16. G. Nikandish, R. B. Staszewski, and A. Zhu, “Design of highly linear broadband continuous mode GaN MMIC power amplifiers for 5G”, IEEE Access, May. 2019
  17. Wang X, Yu C, Li Y, Hong W, Zhu A, “Real-Time Single Channel Over-the-Air Data Acquisition for Digital Predistortion of 5G Massive MIMO Wireless Transmitters”, (IWS), May 2019
  18. K. Pomorski, P. Giounanlis, E. Blokhina, D. Leipold, and R. B. Staszewski, “Unified description of single electron semiconductor devices and Josephson junction devices in the direction of implementation hybrid semiconductor superconductor quantum computer,” Superconductivity in low-dimensional and interacting systems, 3–6 Jun. 2019, pp. 1–1, Physikzentrum, Bad Honnef, Germany
  19. V. O’Brien; B. Mullane, “High Order Mismatch Shaping for Low Oversampling Rates”, (TCAS-II), 2019
  20. V. Nguyen, F. Schembari, R. B. Staszewski, “A 0.2-V 30-MS/s 11b-ENOB Open-Loop VCO-Based ADC in 28-nm CMOS”, IEEE Solid-State Circuits Letters (SSC-L), 2019
  21. M. Hedayati, A. Abdipour, R. Sarraf, M. J. Ammann, M. John, C. Cetintepe, R. B. Staszewski, “Challenges in On-Chip Antenna Design and Integration with RF Receiver Front-End Circuitry in Nanoscale CMOS for 5G Communication Systems”, IEEE Access, March 2019
  22. K. Pomorski, P. Giounanlis, E. Blokhina, D. Leipold, P. Peczkowski, and R. B. Staszewski, “From two types of electrostatic position-dependent semiconductor qubits to quantum universal gates and hybrid semiconductor-superconducting quantum computer,” Superconductivity and Particle Accelerators (SPAS) conference, Proceedings of SPIE, 2019
  23. K. Pomorski, P. Giounanlis, E. Blokhina, D. Leipold, and R. B. Staszewski, “Towards universal framework for electrostaticqubit-based semiconductor quantum computer and its integration with CMOS electronics and superconducting quantum circuits,” Engineering a Scalable Quantum Information Processor, 24 Apr. 2019, pp. 1–1, Physikzentrum, Bad Honnef, Germany
  24. K-F. Un, F. Zhang, P-I. Mak, R. P. Martins, A. Zhu, R. Bogdan Staszewski. “Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas Rejection”, (TCAS-II), March 2019
  25. Y. Hu; T. Siriburanon; R. B. Staszewski, “Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators”, (TCAS-II), 2019
  26. P. Giounanlis, E. Blokhina, K. Pomorski, D. Leipold, and R. B. Staszewski, “Modeling of semiconductor electrostatic qubits realized through coupled quantum dots”, IEEE Access, April. 2019
  27. K. Pomorski, P. Giounanlis, E. Blokhina, R. B. Staszewski, D. Leipold, “Modeling quantum universal gates in semiconductor CMOS,” Scalable Hardware Platforms for Quantum Computing, Jan. 2019
  28. A. Salib; M. F. Flanagan; B. Cardiff, “A Generic Foreground Calibration Algorithm for ADCs with Nonlinear Impairments”, (ISCAS), May 2018
  29. P. Giounanlis ; E. Blokhina ; D. Leipold ; R. B. Staszewski,  “Occupancy Oscillations and Electron Transfer in Multiple-Quantum-Dot Qubits and their Circuit Representation”, (ICECS), 2018
  30. K. Pomorski, P. Giounanlis, E. Blokhina, R. B. Staszewski, “From quantum hardware to quantum AI”, In Proc. of The ShanghAI Lectures, 2018
  31. J. Szyduczyński, V. Nguyen, F. Schembari, R. Bogdan Staszewski, M. Miśkowicz and D. Kościelnik. “Behavioral Modelling and Optimization of a Feedback Successive Approximation TDC with Dynamic Delay Equalization”, EBCCSP June 2018
  32. I. Assom, G. Salgado, D. O’Hare, I. O’Connell, K. O’Donoghue, “A 4th-Order Continuous-Time ΔΣ Modulator with Improved Clock Jitter Immunity using RTZ FIR DAC”, (ICECS), 2018
  33. H. Wang, F. Schembari, M. Miśkowicz, R.B. Staszewski, “An Adaptive-Resolution Quasi-Level-Crossing-Sampling ADC Based on Residue Quantization in 28-nm CMOS”, IEEE Solid-State Circuits Letters (SSC-L), 2018
  34. C. Wilson; J. King, “Ensuring Charge Conservation in GaN HEMT Large Signal Model”, (EuMIC), 2018
  35. M. Keshavarz Hedayati; A. Abdipour; R. Sarraf Shirazi; C. Cetintepe; R. B. Staszewski, “A 33-GHz LNA for 5G Wireless Systems in 28-nm Bulk CMOS”, (TCAS-II), Oct 2018
  36. D. Mai, H. Mo, M.P. Kennedy. Observations and Analysis of Wandering Spurs in MASH-Based Fractional-N Frequency Synthesizers. IEEE Trans. Circuits and Systems-Part II, **(*):***-***, May 2018. (TCAS-II)
  37. G. M. Salgado, A. Dicataldo, D. O’Hare, I. O’Connell, J. M. de la Rosa, “Behavioural Modelling of SAR ADCs in Simulink”, IEEE International Symposium on Circuits and Systems, (ISCAS) May 2018
  38. S. Asghar, S. Afridi, A. Pillai, A. Schuler, J. M. de la Rosa, I. O’Connell, “A 2MS/S, 11.22 ENOB, 3.2 Vpp-D SAR ADC with Improved DNL and Offset Calculation”, IEEE International Symposium on Circuits and Systems, (ISCAS) May 2018
  39. Y. Donnelly, H. Mo and M.P. Kennedy.  High-Speed Nested Cascaded MASH Digital Delta-Sigma Modulator-Based Divider Controller. In Proc. ISCAS 2018, pages ***-***, Florence, **-** May 2018.
  40. P. Chen, F. Zhang, Z. Zong, H. Zheng, T. Siriburanon, R. Bogdan Staszewski.  A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS. IEEE Asian Solid-State Circuits Conference (A-SSCC) Nov 2017.
  41. S. Facchin; S. Zhou; M. Power; A. Jain; C. Scarcella; C. Antony; P. Townsend; P. Ossieur, “A 20Gbaud/s PAM-4 65nm CMOS optical receiver using 3D solenoid based bandwidth enhancement”, IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017
  42. S. Zhou, H. Wu, K. Sadeghipour, C. Scarcella, C. Eason, M. Rensing, M. Power, C. Antony, P. O’Brien, P. Townsend and P. Ossieur, “Optimization of PAM-4 transmitters based on Lumped Silicon Photonic MZMs for High-Speed Short-reach Optical Links”, Optics Express, vol. 25, issue: 4, pp. 4312-4325, Feb 2017
  43. A. Salib, B. Cardiff, M. F. Flanagan, “Blind SAR ADC capacitor mismatch calibration”, Proc. of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug 2017
  44. A. Salib, B. Cardiff, M. F. Flanagan, “A low-complexity correlation-based time skew estimation technique for time-interleaved SAR ADCs”, Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2017
  45. V. Nguyen, F. Schembari, and R. B. Staszewski, “Oscillator-based ADCs: An exploration of time-mode analog-to-digital conversion,” Proc. of IEEE International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP 2017), 24 May 2017, pp. 1–4, Funchal, Madeira, Portugal
  46. H. Mo and M.P. Kennedy. “Influence of Initial Conditions on the Fundamental Periods of LFSR-Dithered MASH Digital Delta-Sigma Modulators with Constant Inputs”. IEEE Trans. Circuits and Systems-Part II, 64(4):372-376, (TCAS-II) Apr 2017.
  47. M.P. Kennedy, H. Mo and D. Mai.  “Nonlinearity-Induced Spurious Tones and Noise in Fractional-N Frequency Synthesizers”, In Proc. URSI Symposium 2017, pages ***-***, Dublin, 8-9 March 2017.
  48. M.P. Kennedy, H. Mo and D. Mai.  “Nonlinearity-Induced Spurious Tones and Noise in Digitally-Assisted Frequency Synthesizers”, In Proc. ISCAS 2017, pages ***-***, Baltimore, **-** May 2017.
  49. S. Galeone and M.P. Kennedy.  “Comparison of Simulation Strategies for Estimating Phase Noise in Oscillators”, In Proc. PRIME 2017, pages ***-***, Taormina, **-** June 2017.
  50. Y. Donnelly and M.P. Kennedy.  “Phase Noise in Fractional-N Frequency Synthesizers Employing Successive Requantizers and MASH-SQ Hybrids”, In Proc. PRIME 2017, pages ***-***, Taormina, **-** June 2017.
  51. D. Mai, H. Mo and M.P. Kennedy.  “Observations of the Differences between Closed-loop Behavior and Feed-forward Model Simulations of Fractional-N Frequency Synthesizers”, In Proc. ISSC 2017, pages ***-***, Tralee, **-** June 2017.
  52. S. Tulisi and M.P. Kennedy. “Performance Limits for Open-Loop Fractional Dividers”, In Proc. ISSC 2017, pages ***-***, Tralee, **-** June 2017.
  53. Kelly, N., Cao, W., and Zhu, A. (2017) ‘Preparing Linearity and Efficiency for 5G: Digital Predistortion for Dual-Band Doherty Power Amplifiers with Mixed-Mode Carrier Aggregation’.  IEEE Microwave Magazine, 18 (1):76-84.
  54. Yu, C., Hou, D., Sun, H., Meng, F., Zhu, X.-W., Zhai, J., Chen, J., and Zhu, A. (2017) A Reconfigurable In-Band Digital Predistortion Technique for mm-Wave Power Amplifiers Excited by a Signal with 640 MHz Modulation Bandwidth The 47th European Microwave Conference (EuMC) Nuremberg, Germany, , 08-OCT-17 – 13-OCT-17
  55. McGrath, K., and Zhu, A. (2017) A 2.0-2.5 GHz Frequency-Selectable Oscillator for Digital Predistortion Model Identification of RF Power Amplifiers The International Workshop on Integrated Nonlinear Microwave and Millimetre-wave Circuits (INMMiC) Graz, Austria, , 20-APR-17 – 21-APR-17
  56. Wang, H., Li, G., Zhang, Y., Liu, F. and Zhu, A. (2017) Forward Modeling Assisted 1-Bit Data Acquisition Based Model Extraction for Digital Predistortion of RF Power Amplifiers IEEE Topical Conference on RF/microwave Power Amplifiers for Wireless and Radio Applications (PAWR) Phoenix, AZ, USA, , 16-JAN-17 – 18-JAN-17
  57. Guo, Y. and Zhu, A. (2017) Power Adaptive Decomposed Vector Rotation Based Digital Predistortion for RF Power Amplifiers in Dynamic Power Transmission IEEE Topical Conference on RF/microwave Power Amplifiers for Wireless and Radio Applications (PAWR) Phoenix, AZ, USA, , 16-JAN-17 – 18-JAN-17
  58. Chen, P, Staszewski, R.B, (2016) “Exponential extended flash time-to-digital converter”, IEEE International Nordic-Mediterranean Workshop on Time-to-Digital Converters and Applications (NoMe – TDC 2016), Krakow, Poland, June, 2016
  59. Xia, J., Yang, M., and Zhu, A. (2016) ‘Improved Doherty Amplifier Design with Minimum Phase Delay in Output Matching Network for Wideband Application’. IEEE Microwave and Wireless Components Letters, 26 (11):915-917.
  60. Liu, S., Lv, N., Ma, H., and Zhu, A. (2016) ‘Adaptive semiblind background calibration of timing mismatches in a two-channel time-interleaved analog-to-digital converter’. Analog Integrated Circuits and Signal Processing, online access. 
  61. Huang, G., Yu, C., and Zhu, A. (2016) ‘Analog Assisted Multichannel Digital Post-Correction for Time-Interleaved ADCs’. IEEE Transactions on Circuits and Systems II: Express Briefs, 63 (8):773-777. (TCAS-II)
  62. Wang, Y., Zhu, A., and Brazil, T. J. (2016) Real-Valued Discrete-Time Impulse Response Representation of Bandpass S-parameters The 46th European Microwave Conference (EuMC) London, UK
  63. Zhu, A. (2016) Behavioral Modeling for Digital Predistortion of RF Power Amplifiers: from Volterra Series to CPWL Functions (invited) IEEE Topical Conference on RF/microwave Power Amplifiers for Wireless and Radio Applications (PAWR) Austin, Texas, USA, , 24-JAN-16 – 27-JAN-16 
  64. D. Mai, H. Mo and M.P. Kennedy. Comments on “Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division.” In Proc. ICECS 2016, pages 1-6, Monaco, 11-14 December 2016 (to appear).
  65. H. Mo, X. Tan and M.P. Kennedy. Maximizing the Fundamental Period of a Dithered Digital Delta-Sigma  Modulator With Constant Input. In Proc. ICECS 2016, pages 1-6, Monaco, 11-14 December 2016 (to appear).
  66. Y. Donnelly and M.P. Kennedy. On the Statistical Properties of Phase Noise in Fractional-N Frequency Synthesizers Using Successive Requantizers. In Proc. ICECS 2016, pages 1-6, Monaco, 11-14 December 2016 (to appear).
  67. A. Marnane, V. Marotta and M.P. Kennedy. Yet Another Spur Mechanism in a Charge-Pump Based Fractional-N PLL. In Proc. ICECS 2016, pages 1-6, Monaco, 11-14 December 2016 (to appear).
  68. Huang G. et al. Analog Assisted Multichannel Digital Postcorrection for Time-Interleaved ADCs. IEEE Trans. Circuits and Systems-Part II, 2016 (in press).
  69. M.P. Kennedy, H. Mo, Z. Huang and J.P. Lana.  A Method to Quantify the Dependence of Spur Heights on Offset Current in a CP-PLL. In Proc. ISCAS 2016, Montreal, 22-25 May 2016.
  70. V. Marotta, G. Macera, M.P. Kennedy and E. Napoli.  Comparative Analysis of Differential Colpitts and Cross-Coupled VCOs in 180nm Si-Ge HBT. In Proc. ISCAS 2016, Montreal, 22-25 May 2016.
  71. H. Mo, G. Hu and M.P. Kennedy.  Comparison of analytical predictions of the noise floor due to static charge pump mismatch in fractional-N frequency synthesizers.  In Proc. ISCAS 2016, Montreal, 22-25 May 2016.
  72. G. Macera, V. Marotta, M.P. Kennedy and E. Napoli. A Back-To-Back Series Varactor Configuration Minimizing the Amplitude-to-Phase Noise Conversion in Si-Ge HBT Technology VCOs. In Proc. ISSC 2016, pages 1-6, Derry, 21-22 June 2016.
  73. D. Mai, H. Mo and M.P. Kennedy. Comparison of the Simulated Performance of Two Successive Requantizers in a Fractional-N Frequency Synthesizer with a Piecewise-Linear Charge-Pump. In Proc. ISSC 2016, pages 1-6, Derry, 21-22 June 2016.
  74. G. Macera, V. Marotta, M.P. Kennedy and E. Napoli. The Low Power and Wide Tuning Range Advantages of Armstrong VCOs in 180 nm Si-Ge HBT Technology. In Proc. ISSC 2016, pages 1-6, Derry, 21-22 June 2016.
  75. H. Mo and M.P. Kennedy. Influence of Initial Conditions on the Fundamental Periods of LFSR-Dithered MASH Digital Delta-Sigma Modulators with Constant Inputs. IEEE Trans. Circuits and Systems-Part II, 2016 (in press). TCAS-II
  1. Iordanov P. et al, “Computation of the Real Structured Singular Value via Pole Migration”, Int. Journal of Robust and Nonlinear Control, 2016.
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