TitleAbstractAuthorsConference / JournalYearDOILink to Publication or Download
Quantum Computer on a Chip," Workshop (1-hr), WSD-8, "Cryogenic Electronics for Quantum Computing and Beyond: Applications, Devices, and Circuits1. R. B. Staszewski, 2021
A 1D-CNN Based Deep Learning Technique for Sleep Apnea Detection in Wearable SensorsA. John, B. Cardiff, D. John, ISCAS, 2021
A Comparative Study of Level-Crossing Sampling Schemes for Event-Driven Electrocardiogram Arrhythmia ClassificationM. Saeed, Q. Wang, O. Märtens, B. Larras, A. Frappé, B. Cardiff, D. John ISCAS, 2021
Continuous User Authentication via the ECG Using IoT Wearable Devices C. Smyth, G. Wang, A. Nag, B. Cardiff, D. John ISCAS, 2021
A 0.02–4.5 GHz LN(T)A in 28-nm CMOS for 5G exploiting noise reduction and current reuseIn this article, a new noise reduction/cancellation technique is proposed to improve noise figure (NF) of a broadband low-noise transconductance amplifier (LNTA) for 5G receivers. The LNTA combines a common-gate (CG) stage for wideband input matching and a common-source (CS) stage for canceling the noise and distortion of the CG stage. Yet, another noise reduction is applied to reduce the channel thermal noise of the noise cancellation stage itself. The technique further exploits current reuse and increases transconductance of the CS transistor while keeping its power consumption low. Fabricated in 28-nm CMOS, the proposed LNTA is capable of driving an external 50- ? load and achieves a NF of 2.09–3.2 dB and input return loss ( S11 ) better than ?10 dB over the 3-dB bandwidth of 20 MHz–4.5 GHz while consuming 4.5 mW from a single 1-V power supply. The achieved gain ( S21 ) and IIP3 are 15.2 dB and ?4.6 dBm, respectively.5. A. Bozorg and R. B. StaszewskiJSSC202110.1109/JSSC.2020.3018680https://ieeexplore.ieee.org/document/9186793
Unbalanced power amplifier: An architecture for broadband back-off efficiency enhancementIn this article, we present a new broadband power amplifier (PA) architecture with a back-off efficiency enhancement that supports very wide modulation bandwidths. The unbalanced PA is composed of two cooperating sub-PAs using the Lange couplers as input power splitter and output power combiner. The PA operation is controlled by the transistors’ width ratio and coupling coefficients of the Lange couplers. The output power back-off (OPBO) level is given by the transistors’ width ratio and coupling coefficient of the output coupler, while the maximum efficiency is achieved at the back-off point. These features provide more design flexibility compared with the conventional Doherty PA, where the OPBO can be set only by the transistors’ width ratio, and the maximum efficiency is achieved at the peak power. Using broadband harmonic matching networks, the main and auxiliary sub-PAs operate in the continuous mode to improve efficiency over a broad bandwidth. A fully integrated unbalanced PA, implemented in a 250-nm GaN-on-SiC process, achieves 32.2–34.3-dBm output power, 27%–37% efficiency at peak power, and 27%–40% at 5–6-dB back-off, across 4.5–6.5 GHz. The PA provides 3.7/4.5% (?28.6/?26.9 dB) rms error vector magnitude (EVM rms ) and 30% average efficiency for a 256-QAM signal with 100-/200-MHz bandwidth, 7.2-dB PAPR, and 25.5-dBm average output power, without using any predistortion.G. Nikandish, R. B. Staszewski and A. Zhu, JSSC202110.1109/JSSC.2020.3014244https://ieeexplore.ieee.org/document/9173563
A Type-II Phase-Tracking ReceiverWe present a new analog-to-digital converter (ADC)-based architecture of a phase-tracking receiver (PT-RX) optimized for ultra-low-power (ULP) and ultra-low-voltage (ULV) operations for the Internet of Things (IoT). The RX employs a type-II loop configuration that offers improved stability compared with the previous type-I PT-RX solutions. In addition, the type-II loop is also very tolerant of long run-lengths of consecutive “1” or “0” symbol sequences. Fabricated in 28-nm CMOS, the prototype PT-RX targets Bluetooth low energy (BLE) standard consuming only 1.5 mW at a supply of ?0.7 V. It maintains an adjacent-channel rejection (ACR) of ??11/3.5/17/27 dB at 0/±1/±2/±3 MHz offset and can tolerate out-of-band (OOB) blockers of minimum ?21 dBm across 1.0–3.5 GHz while also offering a best-in-class figure of merit (FoM) of 181 dB, with a 1-Mb/s BLE sensitivity of ?93 dBm. S. Hu, J. Du, P. Chen, H. M. Nguyen, P. Quinlan and R. B. StaszewskiJSSC202110.1109/JSSC.2020.3005797https://ieeexplore.ieee.org/document/9143443
Planar High Frequency Magnetic Material Large Signal Measurement and Performance Factor Comparisons for Planar Toroidal Inductors Embedded in PCB R. Murphy et al, APEC, 2021
An Active-under-Coil RFDAC with Analog Linear Interpolation in 28-nm CMOSThis paper demonstrates a wideband 2.4 GHz 2x 9-bit Cartesian radio-frequency digital-to-analog converter (RFDAC). Active-under-coil integration is introduced in the physical implementation, where all key active circuitry is located underneath the matching-network transformer, achieving a core area of merely 0.35 mm². An 8x analog linear interpolation at the RF rate is proposed to suppress replicas close to the carrier while avoiding any high-order and high-speed digital filters in digital processing back-end. The multi-port transformer is adopted in the matching network to improve the back-off efficiency. The measured peak output power and drain efficiency at the center frequency of 2.4 GHz are 17.47 dBm and 17.6% respectively, while the peak efficiency is 19.03%. Moreover, the 6-dB back-off efficiency is at 66% of that at the peak output power. The active-under-coil integration helps this RFDAC to achieve the smallest area among comparable prior arts.F. Zhang, P. Chen, J. S. Walling, A. Zhu, R.B. StaszewskiTCAS-I202110.1109/TCSI.2021.3059368https://ieeexplore.ieee.org/document/9361220
Oscillator flicker phase noise: A tutorialA deep understanding of how to reduce flicker phase noise (PN) in oscillators is critical in supporting ultra-low PN frequency generation for the advanced communications and other emerging high-speed applications. Unfortunately, the current literature is either full of conflicting theories and ambiguities or too complex in mathematics, hiding the physical insights. In this brief, we comprehensively review the evolution of flicker noise upconversion theories and clarify their controversial and confusing parts. Two classes of such upconversion mechanisms in voltage-biased LC -tank oscillators (nMOS-only and complementary) are specifically compared and numerically verified using a commercial simulation model of 28-nm CMOS. We identify that non-resistive terminations of both 2nd and 3rd harmonic currents contribute to oscillation waveform asymmetries that lead to the flicker noise upconversion. Further, we discuss three 1/f3 PN reduction mechanisms: waveform shaping, narrowing of conduction angle, and gate-drain phase shift.Y. Hu, T. Siriburanon and R. B. StaszewskiTCAS-II, 202110.1109/TCSII.2020.3043165https://ieeexplore.ieee.org/document/9286468
A fully integrated GaN dual-channel power amplifier with crosstalk suppression for 5G massive MIMO transmittersWe present a broadband dual-channel power amplifier (PA) with crosstalk suppression for multi-input multi-output (MIMO) communications. Operation of MIMO system with crosstalk is theoretically evaluated for two popular coding schemes including the space-time coding and linear precoding. Design challenges of a multi-channel PA on a single chip are investigated and circuit techniques, including second-harmonic trapping integrated into the output matching network and the use of back-via lines to isolate the channels, are proposed to mitigate the inter-channel crosstalk. A fully integrated dual-channel PA prototype, implemented using a 250-nm GaN-on-SiC process, provides 34.9–36.3dBm output power, 44–49% power-added efficiency (PAE), 11.3–12.3 dB power gain, 31.0–34.2 dB second-harmonic rejection, and ?28.1 dB to ?25.7 dB inter-channel crosstalk across 4.5–6.5 GHz. For a 100-MHz 256-QAM signal with 7.2 dB peak-to-average power ratio (PAPR), the PA achieves 29.9dBm average output power, 30% average PAE, ?38.2/?39.1 dBc adjacent channel leakage ratio (ACLR), and ?28.2 dB (3.9%) rms error vector magnitude (EVM), without using digital predistortion (DPD). Effect of crosstalk on linearity of the dual-channel PA is also measured and it is shown that for a 256-QAM signal EVM can increase by 3–8 dB, depending on relative power levels of the two channels. G. Nikandish, R. B. Staszewski and A. ZhuTCAS-II,202110.1109/TCSII.2020.3008365
https://ieeexplore.ieee.org/document/9138457
MASH-Based Divider Controllers for Mitigation of Wandering Spurs in a Fractional-N Frequency SynthesizerThe divider controller can contribute significantly to the phase noise and spur pattern in the output of a nonlinear fractional-N frequency synthesizer. A type of time-varying spurs caused by a MASH DDSM divider controller, termed wandering spurs, has been observed in simulations and measurements of real synthesizers. In this work, we propose and analyze several MASH-based divider controller architectures that mitigate wandering spurs in a fractional-N frequency synthesizer.D. Mai, M. P. KennedyTCAS-I, 202110.1109/TCSI.2020.3035538https://ieeexplore.ieee.org/document/9264725
Position-based CMOS charge qubits for scalable quantum processors at 4KWe describe a quantum computing hardware paradigm that exploits the current scaling achievements of mainstream CMOS technology. Just like in a small IC chip, where a single nanometer-sized CMOS transistor can be reliably replicated millions of times to build a digital processor, we propose a new structure of a qubit realized as a CMOS-compatible charge-based quantum dot that can be reliably replicated thousands (or perhaps even millions) of times to construct a quantum processor. Combined with an on-chip CMOS controller, it will realize a useful quantum computer (QC) that can operate at 4 K, which is much higher than the temperature of today's QCs of 15 mK.R. B. Staszewski, P. Giounanlis, A. Esmailiyan, H. Wang, I. Bashir, C. Cetintepe, D. Andrade-Miceli, M. Asker, D. Leipold, T. Siriburanon, A. Sokolov and E. BlokhinaISCAS202010.1109/ISCAS45731.2020.9180789https://ieeexplore.ieee.org/document/9180789
Electrostatic control and entanglement of CMOS position-based qubitsIn this paper we demonstrate electrostatic control and feasibility of entanglement in CMOS qubits. We present both single particle and multi-particle methodologies to describe quantum transport using a time-dependent Hamiltonian assuming one spatial degree of freedom. The developed models predict maximally entangled states of electrons controlled electrostatically by external driving fields and interacting via the Coulomb force. P. Giounanlis, A. Sokolov, E. Blokhina, I. Bashir, D. Leipold and R. B. StaszewskiISCAS,202010.1109/ISCAS45731.2020.9180721https://ieeexplore.ieee.org/document/9180721
Design of Ultra-Low-Power Discrete-time Receivers for the Internet of Things Mini- tutorial (2-hrs)S. Binsfeld-Ferreira and R. B. StaszewskiISCAS2020
A 0.02-4.5-GHz LN(T)A in 28-nm CMOS for 5G Exploiting Noise Reduction and Current Reuse”,In this article, a new noise reduction/cancellation technique is proposed to improve noise figure (NF) of a broadband low-noise transconductance amplifier (LNTA) for 5G receivers. The LNTA combines a common-gate (CG) stage for wideband input matching and a common-source (CS) stage for canceling the noise and distortion of the CG stage. Yet, another noise reduction is applied to reduce the channel thermal noise of the noise cancellation stage itself. The technique further exploits current reuse and increases transconductance of the CS transistor while keeping its power consumption low. Fabricated in 28-nm CMOS, the proposed LNTA is capable of driving an external 50-? load and achieves a NF of 2.09-3.2 dB and input return loss (S??) better than -10 dB over the 3-dB bandwidth of 20 MHz-4.5 GHz while consuming 4.5 mW from a single 1-V power supply. The achieved gain (S??) and IIP3 are 15.2 dB and -4.6 dBm, respectively.A. Bozorg, R. B. StaszewskiJSSC202010.1109/JSSC.2020.3018680https://ieeexplore.ieee.org/document/9186793
A fully integrated DAC for CMOS position-based charge qubits with single-electron detector loopback testing”This letter presents a fully integrated interface circuitry with a position-based charge qubit structure implemented in 22-nm FDSOI CMOS. The quantum structure is controlled by a tiny capacitive DAC (CDAC) that occupies 3.5×45?m2 and consumes 0.27mW running at a 2-GHz system clock. The state of the quantum structure is measured by a single-electron detector that consumes 1mW (including its output driver) with an area of 40×25?m2 . The low power and miniaturized layout of these circuits pave the way for integration in a large quantum core with thousands of qubits, which is a necessity for practical quantum computers. The CDAC output noise of 12 ?V -rms is estimated through mathematical analysis while the ? 0.225mV-rms input referred noise of the detector is verified by measurements at 3.4 K. The functionality of the system and performance of the CDAC are verified in a loopback mode with the detector sensing the CDAC-induced electron tunneling from the floating diffusion node into the quantum structure.A. Esmailiyan, H. Wang, M. Asker, E. Koskin, D. Leipold, I. Bashir, K. Xu, A. Koziol, E. Blokhina, and R. B. StaszewskiSSC-L202010.1109/LSSC.2020.3018707https://ieeexplore.ieee.org/document/9174663
A Low-Power 1-V Supply Dynamic ComparatorThis letter presents a low-power dynamic comparator for ultralow power applications. The prototype is designed in a 65-nm CMOS process with a supply voltage of 1 V and is compared against the widely used double tail latch comparator in terms of power consumption and input referred rms noise. The addition of cross-coupled devices to the input differential pair prevents the comparator internal nodes from fully discharging to ground in contrast to the conventional architecture. This reduces the power consumption while achieving similar noise levels. Measurements demonstrate that the proposed comparator achieves an input referred rms noise voltage of 220 ?V against 210 ?V for the conventional comparator with a 30% reduction in power. The proposed circuit consumes 0.19-pJ energy per comparison.Chevella, S, O’Hare, D and O’Connell, SSC-L202010.1109/LSSC.2020.3009437https://ieeexplore.ieee.org/document/9141323
A tiny complementary oscillator with noise reduction using a triple-8-shaped transformerThis letter presents a triple-8-shaped transformer-based complementary oscillator. It features tiny area, wide tuning range (TR), electromagnetic compatibility (EMC), and low flicker phase noise (PN), combining the merits of both LC -tank and ring oscillators. We identify that after suppressing the second-harmonic voltage by the complementary operation itself, the third-harmonic current entering the capacitive path is now the main cause of asymmetry in the rising and falling edges, leading to the 1/f noise upconversion. By tuning the capacitance ratio between gate and drain nodes of the switching transistors, it mitigates the third-harmonic voltage and introduces a specific gate–drain phase shift, reducing the 1/f3 PN. Fabricated in 22-nm FDSOI CMOS, the prototype occupies an area of 0.01 mm 2 and achieves 1/f3 PN corner of 70 kHz, PN of ?110 dBc/Hz @1MHz and Figure-of-Merit (FoM) of ?182 dB at 9 GHz, 39% TR, resulting in the best FoM with normalized TR and area (FoM TA ) of ?214 dB@1 MHz.X. Chen, Y. Hu, T. Siriburanon, J. Du, R. B. Staszewski, and A. ZhuSSC-L, 202010.1109/LSSC.2020.3009205https://ieeexplore.ieee.org/document/9139997
A 2.0–2.87GHz -249dB FoM 1.1 mW digital PLL exploiting reference-sampling phase detectorJ. Du, T. Siriburanon, Y. Hu, V. Govindaraj, and R. B. StaszewskiSSC-L2020
A 0.01mm2 0.83V Input Range SAR Based Bridge-to-Digital ConverterThis letter presents a compact buffer-less 12-bit output SAR-based bridge-to-digital converter. Eliminating the sample-and-hold circuit substantially simplifies the sensor front-end by providing a high-impedance input stage. The binary weighted digital-to-analog converter (DAC) is replaced with a switched-capacitor DAC which is driven by an error-feedback modulator. This alleviates mismatch issues and provides area and power savings when used with a Wheatstone bridge as a read-out. The converter has a wide input range of 830 mV making it suitable for gas sensor applications. It is realized in 65-nm CMOS, occupies 0.01 mm 2 area, and consumes 6.2 ?A with a 45 ms conversion time. It achieves 9.1 ENOB for a DC input and a Walden FoM of 0.65 nJ/conv-step.A. Fordymacka et alSSC-L202010.1109/LSSC.2020.3018427https://ieeexplore.ieee.org/document/9183905
Modeling and Analysis of Error Feedback Noise-Shaping SAR ADCsThis paper presents behavioural modelling and analysis of Error Feedback (EF) SAR ADCs. The capacitor array model proposed here is based in charge equations, which allows accurate modelling of the feedback in EF-SARs. It also introduces models for the feedback amplifier, including offset, non-linear gain, thermal and flicker noise, as well as sampled kT/C noise for switches and reference noise. The proposed models are implemented and validated in Matlab¯ Simulink¯, showing results with accuracy comparable to transistor-level simulations and simulation times several orders of magnitude faster.7. G. M. Salgado, D. O'Hare, and I. O'ConnellISCAS202010.1109/ISCAS45731.2020.9180995https://ieeexplore.ieee.org/document/9180995
A Generalized Signal Quality Estimation Method for IoT SensorsIoT wearable devices are widely expected to reduce the cost and risk of personal healthcare. However, ambulatory data collected from such devices are often corrupted or contaminated with severe noises. Signal Quality Indicators (SQIs) can be used to assess the quality of data obtained from wearable devices, such that transmission/ storage of unusable data can be prevented. This article introduces a novel and generalized SQI which can be implemented on an edge device for detecting the quality of any quasi-periodic signal under observation, regardless of the type of noise present. The application of this SQI on Electrocardiogram (ECG) signals is investigated. From the analysis carried out, it was found that the proposed generalized SQI is suitable for quality assessment of ECG signals and exhibits a linear behavior in the medium to high SNR regions under all noise conditions considered. The proposed SQI was used for acceptability testing of ECG records in CinC Physionet 2011 challenge dataset and found to be accurate for 90.4% of the records while having minimal computational complexity.A. John, B. Cardiff, D. JohnISCAS202010.1109/ISCAS45731.2020.9180546https://ieeexplore.ieee.org/document/9180546
A Type-II Phase-Tracking ReceiverWe present a new analog-to-digital converter (ADC)-based architecture of a phase-tracking receiver (PT-RX) optimized for ultra-low-power (ULP) and ultra-low-voltage (ULV) operations for the Internet of Things (IoT). The RX employs a type-II loop configuration that offers improved stability compared with the previous type-I PT-RX solutions. In addition, the type-II loop is also very tolerant of long run-lengths of consecutive ``1'' or ``0'' symbol sequences. Fabricated in 28-nm CMOS, the prototype PT-RX targets Bluetooth low energy (BLE) standard consuming only 1.5 mW at a supply of ?0.7 V. It maintains an adjacent-channel rejection (ACR) of ?-11/3.5/17/27 dB at 0/±1/±2/±3 MHz offset and can tolerate out-of-band (OOB) blockers of minimum -21 dBm across 1.0-3.5 GHz while also offering a best-in-class figure of merit (FoM) of 181 dB, with a 1-Mb/s BLE sensitivity of -93 dBm.S. Hu, J. Du, P. Chen, H. M. Nguyen, P. Quinlan, B. StaszewskiJSSC202010.1109/JSSC.2020.3005797https://ieeexplore.ieee.org/document/9143443
A 21.7-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency Tracking Loop Achieving 75fs Jitter and -250dB FoMSub-sampling (SS) and injection-locking (IL) techniques are becoming increasingly popular for 5G millimeter-wave (mmW) frequency generation [1], [2] due to their ability to achieve ultra-low jitter (<; 100fs). However, as indicated in Fig. 17.6.1 (top-left), sub-sampling PLLs (SS-PLL) typically suffer from high-power consumption, especially in mmW VCO buffers, which isolate the VCO from its sampler for reducing reference spurs, and in the high-speed dividers [2]-[4]. Also, the analog loop filter usually occupies large area. On the other hand, the IL technique for mmW frequency generation requires power-hungry high-frequency injection (~GHz) to fully suppress the oscillator phase noise [1], [4] and cannot ensure robustness over PVT (process, voltage, temperature) [4], which requires an additional frequency-tracking loop (FTL), see Fig. 17.6.1 (top-right). Furthermore, there exists a significant danger of a timing-race problem between the injection reference and FTL, since the frequency error may be corrected by IL before the FTL senses it. In [1], the FTL based on a phase averaging technique can solve the timing-race problem but requires a QVCO and an analog loop filter with relatively large area. Y. Hu, X. Chen, T. Siriburanon, J. Du, Z. Gao, V. Govindaraj, A. Zhu, R. B. StaszewskiISSCC202010.1109/ISSCC19947.2020.9063024https://ieeexplore.ieee.org/document/9063024
An event-driven quasi-level-crossing delta modulator based on residue quantizationThis article introduces a digitally intensive eventdriven quasi-level-crossing (quasi-LC) delta-modulator analogto-digital converter (ADC) with adaptive resolution (AR) for Internet of Things (IoT) wireless networks, in which minimizing the average sampling rate for sparse input signals can significantly reduce the power consumed in data transmission, processing, and storage. The proposed AR quasi-LC delta modulator quantizes the residue voltage signal with a 4-bit asynchronous successive-approximation-register (SAR) sub-ADC, which enables a straightforward implementation of LC and AR algorithms in the digital domain. The proposed modulator achieves data compression by means of a globally signal-dependent average sampling rate and achieves AR through a digital multi-level comparison window that overcomes the tradeoff between the dynamic range and the input bandwidth in the conventional LC ADCs. Engaging the AR algorithm reduces the average sampling rate by a factor of 3 at the edge of the modulator's signal bandwidth. The proposed modulator is fabricated in 28-nm CMOS and achieves a peak SNDR of 53 dB over a signal bandwidth of 1.42 MHz while consuming 205 ?W and an active area of 0.0126 mm 2H. Wang, F. Schembari, and R. B. StaszewskiJSSC202010.1109/JSSC.2019.2950175https://ieeexplore.ieee.org/document/8894456
A 31-? W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOSThis article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold comparator. The DTC operation mechanism is analyzed and design tradeoffs are investigated. The proposed DTC consumes merely 31 ?W from a 1-V supply when clocked at 40 MHz, while achieving a fine resolution of 148 fs over a 9-bit range. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.96/1.07 LSB.Chen P, Zhang F, Zong Z, Hu S, Siriburanon T, Staszewski RBJSSC202010.1109/JSSC.2019.2939663https://ieeexplore.ieee.org/document/8850049
Ultra-Wideband Dual-Mode Doherty Power Amplifier Using Reciprocal Gate Bias for 5G ApplicationsA novel architecture to extend the bandwidth of the Doherty power amplifier (DPA) is presented in this article. It is illustrated that two DPA modes at different frequency bands can be realized by simply swapping the gate biases of the transistors without changing the matching circuits, and hence, ultrawide bandwidth can be achieved by using a single load modulation network in DPA. A dual-mode DPA with 2.8-4.1-GHz bandwidth for Mode I and 2.2-2.7-GHz/4.2-4.8-GHz bandwidth for Mode II using commercial GaN transistors is designed and implemented to validate the proposed architecture. The fabricated DPA attains a measured 7.5-11.7-dB gain and 39.2-41-dBm saturated power. 35.0%-49.7% drain efficiency is obtained at 6-dB output power back-off for the designed dual-mode bands. When driven by a ten-carrier 200-MHz OFDM signal with 7.7-dB peak-to-average power ratio, the proposed DPA achieves adjacent channel leakage ratio of better than -50 dBc after digital predistortion at 2.5 GHz/3.5 GHz/4.5 GHz with an average efficiency of 46.0%/35.7%/33.0%. This simple configuration provides a promising solution for 5G, where multiple frequency bands in sub-6 GHz will be deployed. Li M, Pang J, Li Y, Zhu AMTT202010.1109/TMTT.2019.2932977https://ieeexplore.ieee.org/document/8798891
Influence of Initial Condition on Wandering Spur Pattern in a MASH-Based Fractional-N Frequency SynthesizerA Multi-stAge noiSe sHaping Digital Delta-Sigma Modulator (MASH DDSM) is commonly employed as the divider controller in a fractional-N frequency synthesizer. Previous work has considered a time-varying pattern of spurious tones, called wandering spurs, which originate in the DDSM. Two cases have been considered, namely when the fractional part of the division ratio is (i) close to zero or (ii) close to a simple fraction. In both cases, the wandering spur pattern is independent of the initial state of the modulator. This brief considers a third case where the pattern of wandering spurs depends explicitly on the initial state. The phenomenon is explained analytically and simulation results are presented. Theoretical predictions are confirmed with spectral measurements from a representative commercial monolithic fractional-N frequency synthesizer.D. Mai, M. P. KennedyTCAS-II202010.1109/TCSII.2020.2985640https://ieeexplore.ieee.org/document/9056837
Recent Advances and Trends in Noise Shaping SAR ADCsThis brief presents an overview of the recent advances in noise shaping SAR ADCs. It discusses the fundamentals behind the noise shaping operation and the two main implementation topologies. Error feedback and cascaded integrators feedforward topologies are examined. Active and passive circuit level implementations, with emphasis in deep nanometre CMOS processes, are discussed along with the associated design trade-offs. Trends in the area such as multi-stage and cascaded implementations are also discussed.G.M. Salgado, D. O’Hare, I. O’ConnellTCAS-II202010.1109/TCSII.2020.3046170https://ieeexplore.ieee.org/document/9300225
Broadband Fully Integrated GaN Power Amplifier With Minimum-Inductance BPF Matching and Two-Transistor AM-PM CompensationIn this paper, we present a design technique for broadband fully integrated GaN power amplifiers (PAs), with merged bandpass filter (BPF) and AM-PM compensation. The minimum-inductance BPF structure is used as the output matching network of the PA. A new theory of the minimum-inductance BPF is developed and it is shown that, compared to the standard BPF, it can be implemented using lower total inductance and provide higher out-of-band attenuation. Furthermore, using a two-transistor architecture, an AM-PM compensation technique is proposed where compressive and expansive nonlinearity profiles of the transistors' transconductance and gate-source capacitance are combined to achieve a linear total transconductance and input capacitance, over a wide power range. A fully integrated PA prototype, implemented in a 0.25-?m GaN-on-SiC process with 28-V supply, provides 35.1-38.9dBm output power, 45-61% drain efficiency (DE), 40-55% power-added efficiency (PAE), and 11.3-13.4dB power gain, across 2.0-4.0GHz. For a 256-QAM signal with 7.2-dB PAPR and 100-MHz bandwidth at 2.4GHz, it achieves 2.5% (-32.0dB) rms error vector magnitude (EVMrms) and -37.5/-37.6dBc adjacent channel leakage ratio (ACLR), while average output power and DE/PAE are respectively 30.1dBm and 20.6/19.5%, without predistortion. EVMrms and ACLR can be improved to 0.5% (-46dB) and -46.4/-46.8dBc by using digital predistortion (DPD). G. Nikandish, R. B. Staszewski and A. ZhuTCAS-I202010.1109/TCSI.2020.3002395https://ieeexplore.ieee.org/document/9122396
An adaptive-resolution quasi-level-crossing Delta modulator with VCO-based residue quantizerThis brief introduces an adaptive-resolution (AR) quasi-level-crossing delta modulator ADC with a voltage-controlled oscillator (VCO)-based residue quantizer for Internet-of-Things (IoT) wireless sensor nodes. The residue voltage signal is digitized by a VCO-based residue quantizer, thus leading to a straightforward implementation of level-crossing (LC) and AR algorithms in digital domain. The inherent and mismatch-induced dithering provided by the VCO-based residue quantizer increases the proposed modulator's dynamic range and average sampling rate for slowly-varying input signals, enabling accurate sampling and conversion. For fast-varying signals, the AR algorithm is adopted to reduce the average sampling rate by a factor of three compared to the straightforward LC algorithm at the edge of the modulator's signal bandwidth. Fabricated in 28-nm CMOS, the proposed modulator achieves a peak SNDR of 53dB over a signal bandwidth of 1.78MHz.H. Wang, V. Nguyen, F. Schembari, and R. B. StaszewskiTCAS-II202010.1109/TCSII.2020.2979078https://ieeexplore.ieee.org/document/9026813
A 0.36-V 5-MS/s time-mode flash ADC with Dickson-charge-pump-based comparators in 28-nm CMOSDickson charge-pump (CP) is proposed here to realize a voltage-to-time converter (VTC) within an array of time-domain comparators of a 54-level time-mode subthreshold flash ADC operating at 0.36V. Two identical CPs in each of the 54 ADC slices convert the input and reference voltages into variable-slope ramp signals fed into comparators for `flash' quantization. Considering the fact that the comparator's evaluation time gets severely degraded at subthreshold input voltages, the proposed ADC delivers the maximum bandwidth by means of the inherent input voltage boosting by the Dickson CPs. The proposed architecture quantizes the analog input signal into time with CPs and then into digital domain with latches and simple logic, without using any analog-intensive circuits such as amplifiers and current sources, thus yielding a digitally friendly implementation. Measurement results show peak ENOB of 5.04-bit, SNDR of 32.1dB at the peak, power consumption of 88 ?W . The conversion rate of 5 MS/s is the highest among near- and subthreshold ADCs.A. Esmailiyan, F. Schembari, and R. B. Staszewski, TCAS-I202010.1109/TCSI.2020.2969804https://ieeexplore.ieee.org/document/8985311
Mitigation of “Horn Spurs” in a MASH-Based Fractional-N CP-PLLA Fractional-N Charge Pump (CP) PLL with a Multi-stAge noise SHaping (MASH) 1-1-1 divider controller has been reported to exhibit pairs of spurious tones called “horn spurs”. The phenomenon has been confirmed in measurements on a commercial wideband synthesizer. This brief presents an analysis of the phenomenon and techniques to mitigate it. MATLAB simulation results are presented for a type-II CP-PLL with a third order MASH Digital ?? Modulator (DDSM) to validate the techniques that are shown. Measurement results are also presented. V. Mazzaro, M. P. KennedyTCAS-II202010.1109/TCSII.2020.2984359https://ieeexplore.ieee.org/document/9051993
Analysis of Wandering Spur Patterns in a Fractional-N Frequency Synthesizer with a MASH-Based Divider Controller
The Multi-stAge noise SHaping Digital Delta-Sigma Modulator (MASH DDSM), which is commonly used as a divider controller in a fractional-N frequency synthesizer, can produce a time-varying periodic pattern of tones in the output spectrum of the synthesizer; these are known as wandering spurs. In this work, a detailed analysis of the cause of wandering spur patterns in a MASH 1-1-1 DDSM-based fractional-N frequency synthesizer, supported by experimental measurements, is presente D. Mai, M. P. KennedyTCAS-I202010.1109/TCSI.2019.2958781https://ieeexplore.ieee.org/abstract/document/8948345
Jitter Minimization in Digital PLLs with Mid-Rise TDCsThis paper analyzes the absolute jitter performance of digital phase-locked loops and compares the case when either a multi-bit time-to-digital converter with mid-rise characteristic or a bang-bang phase detector is adopted. The linear equivalent model of the PLL and expressions for random-noise and limitcycle jitter are first derived for the case of a 2-bit time-to-digital converter with a mid-rise characteristic, and the optimal TDC resolution is determined. The analysis, which account for TDC mismatches, shows that, compared to the 1-bit one, the 2-bit time-to-digital converter can substantially reduce the quantization noise in the case of dominant random-walk noise at the TDC input. Moving to the N b -bit midrise TDC case, the quantization noise can be further reduced at the cost of higher complexity and finer time resolution. The choice of N b = 2 seems to be the best compromise between jitter reduction and complexity increase. Time-domain simulations assess the theoretical framework and demonstrate the validity of the assumptions made throughout the paperL. Avallone, M. P. Kennedy, S. Karman, C. Samori, S. LevantinoTCAS-I202010.1109/TCSI.2019.2959252https://ieeexplore.ieee.org/document/8946565
Time-skew estimation for random sampling sequence time-interleaved ADCsThis brief proposes a closed-loop architecture which performs background calibration of time-skew mismatch in time-interleaved ADCs (TIADCs). The proposed scheme is tailored to work with the use of a random sampling sequence (RSS) which can provide an improvement in the SFDR without incurring a penalty in the SNDR. The calibration algorithm places some constraints on the random sampling sequence, which are satisfied via a proposed sequence generation algorithm based on a linear-feedback shift register (LFSR). We also show how the timing reference can be selected so as to reduce the requirements of the time-skew correction circuit, and we demonstrate the resulting production yield improvements. The proposed algorithm was synthesized for a TIADC composed of 9 sub-ADCs having an aggregated sampling rate of 2.4GS/sec in a 28nm process; the design occupies 0.014mm 2 and consumes 2.93mW. We demonstrate that the proposed algorithm successfully compensates the time-skew mismatch, allowing to achieve SFDR above 100dB.A. Salib, B. Cardiff, M. F. FlanaganTCAS-II, 202010.1109/TCSII.2019.2956101https://ieeexplore.ieee.org/document/8913532
An Adaptive-Resolution Quasi-Level-Crossing Delta Modulator With VCO-Based Residue QuantizerThis brief introduces an adaptive-resolution (AR) quasi-level-crossing delta modulator ADC with a voltage-controlled oscillator (VCO)-based residue quantizer for Internet-of-Things (IoT) wireless sensor nodes. The residue voltage signal is digitized by a VCO-based residue quantizer, thus leading to a straightforward implementation of level-crossing (LC) and AR algorithms in digital domain. The inherent and mismatch-induced dithering provided by the VCO-based residue quantizer increases the proposed modulator’s dynamic range and average sampling rate for slowly-varying input signals, enabling accurate sampling and conversion. For fast-varying signals, the AR algorithm is adopted to reduce the average sampling rate by a factor of three compared to the straightforward LC algorithm at the edge of the modulator’s signal bandwidth. Fabricated in 28-nm CMOS, the proposed modulator achieves a peak SNDR of 53dB over a signal bandwidth of 1.78MHz. H. Wang, V. Nguyen, F. Schembari, and R. B. StaszewskiTCAS-II202010.1109/TCSII.2020.2979078https://ieeexplore.ieee.org/document/9026813
A 0.36-V 5-MS/s time-mode flash ADC with Dickson-charge-pump-based comparators in 28-nm CMOSDickson charge-pump (CP) is proposed here to realize a voltage-to-time converter (VTC) within an array of time-domain comparators of a 54-level time-mode subthreshold flash ADC operating at 0.36V. Two identical CPs in each of the 54 ADC slices convert the input and reference voltages into variable-slope ramp signals fed into comparators for `flash' quantization. Considering the fact that the comparator's evaluation time gets severely degraded at subthreshold input voltages, the proposed ADC delivers the maximum bandwidth by means of the inherent input voltage boosting by the Dickson CPs. The proposed architecture quantizes the analog input signal into time with CPs and then into digital domain with latches and simple logic, without using any analog-intensive circuits such as amplifiers and current sources, thus yielding a digitally friendly implementation. Measurement results show peak ENOB of 5.04-bit, SNDR of 32.1dB at the peak, power consumption of 88 ?W . The conversion rate of 5 MS/s is the highest among near- and subthreshold ADCsA. Esmailiyan, F. Schembari, and R. B. StaszewskiTCAS-I202010.1109/TCSI.2020.2969804https://ieeexplore.ieee.org/document/8985311
Time-Skew Estimation for Random Sampling Sequence Time-Interleaved ADCsThis brief proposes a closed-loop architecture which performs background calibration of time-skew mismatch in time-interleaved ADCs (TIADCs). The proposed scheme is tailored to work with the use of a random sampling sequence (RSS) which can provide an improvement in the SFDR without incurring a penalty in the SNDR. The calibration algorithm places some constraints on the random sampling sequence, which are satisfied via a proposed sequence generation algorithm based on a linear-feedback shift register (LFSR). We also show how the timing reference can be selected so as to reduce the requirements of the time-skew correction circuit, and we demonstrate the resulting production yield improvements. The proposed algorithm was synthesized for a TIADC composed of 9 sub-ADCs having an aggregated sampling rate of 2.4GS/sec in a 28nm process; the design occupies 0.014mm 2 and consumes 2.93mW. We demonstrate that the proposed algorithm successfully compensates the time-skew mismatch, allowing to achieve SFDR above 100dB A. Salib, B. Cardiff, M. F. FlanaganTCAS-II202010.1109/TCSII.2019.2956101https://ieeexplore.ieee.org/document/8913532
Broadband fully integrated GaN power amplifier with embedded minimum inductor bandpass filter and AM-PM compensationIn this letter, we present a design technique for broadband linearized fully integrated GaN power amplifiers (PAs). The minimum inductor bandpass filter structure is used as the output matching network to achieve low loss and high out-of-band attenuation. Two parallel transistors with unbalanced gate biases are used to mitigate nonlinearity of their transconductance and input capacitance, and consequently, compensate AM-PM distortion of the PA. A fully integrated GaN PA prototype provides 35.1-38.9-dBm output power and 40%-55% power-added efficiency (PAE) in 2.0-4.0 GHz. For a 64-QAM signal with 8-dB peak-to-average power ratio (PAPR) and 100-MHz bandwidth at 2.4 GHz, average output power of 32.7 dBm and average PAE of 31% are measured with -30.2-dB error vector magnitude (EVM).G. Nikandish, R. B. Staszewski, and A. ZhuESSCIRC201910.1109/LSSC.2019.2927855https://ieeexplore.ieee.org/document/8758912
4.48-GHz Fractional- N Frequency Synthesizer With Spurious-Tone Suppression via Probability Mass RedistributionA 4.48-GHz type-II charge pump fractional-N PLL implemented in a 0.18-?m BiCMOS process is presented. The divider controller's output is processed using a novel block, the probability mass redistributor, which statistically reconfigures the modulation noise such that fractional spurs are minimized. Measurements demonstrate in-band fractional spurs of -80 dBc. The solution, which is a drop-in modification of a conventional MASH structure, incurs a modulator area increase of 22%, and can be used in conjunction with other linearization strategies. Y. Donnelly, M. P. Kennedy, J. Breslin, S. Tulisi, S. Patil, C. Curtin, S. Brookes, B. Shelly, P. Griffin, M. KeaveneySSC-L201910.1109/LSSC.2019.2943936https://ieeexplore.ieee.org/document/8850113
A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling MitigationIn this paper, we propose a sub-gigahertz transmitter (TX) with a physically merged digitally controlled oscillator (DCO) and digital power amplifier (DPA). The matching transformer of single-ended DPA is placed inside the DCO transformer to save ~50% of area. The resulting DCO pulling is compensated via a feedback path and an inter-winding cancellation capacitor suppresses the second harmonic. Fabricated in 16-nm FinFET CMOS, the DPA reaches 51% efficiency at 11-dBm output with <; -55-dBc HD 2 . The 1.8-GHz DCO exhibits -116-dBc/Hz phase noise (PN) at 1-MHz offset and draws 195 uW from 0.3-V supply. The error vector magnitude measured with a 2-MHz 64-Quadratic amplitude modulation (QAM) orthogonal frequency division multiplexing signal at 5-dBm average power is 3.7%.17. K. Xu; F. Kuo; H. R. Chen; L. Cho; C. Jou; M. Chen; R. B. StaszewskiJSSC201910.1109/JSSC.2019.2906803https://ieeexplore.ieee.org/document/8695781
A 0.3 V, 35% tuning-range, 60 kHz 1/f3-corner digitally controlled oscillator with vertically integrated switched capacitor banks achieving FoMT of -199 dB in 28-nm CMOSWe present a sub-mW ultra-low-voltage (ULV) digitally controlled oscillator (DCO) in which all electronic devices (amplifying transistors and switched-capacitor banks) are vertically embedded within the inductor coils. A special arrangement of native layer (NT N) diminishes any adverse effects on the inductors. To suppress flicker noise upconversion while maintaining wide tuning range (TR), we propose a technique of reduced current conduction angle. Its robust start-up is ensured by a passive gain of the proposed high-km 2:3 transformer, which is an advantage over the current approaches in class-C oscillators. Implemented in 28-nm CMOS, the proposed DCO achieves -95 dBc/Hz and -118 dBc/Hz at 100 kHz and 1 MHz offsets, respectively. The measured 1/f3 corner is from 60 kHz to 100 kHz over the 35% TR (from 2.02 GHz to 2.87 GHz). This results in a figure-of-merit with normalized TR (FoMT) at 100 kHz and 1 MHz offsets of -196 dB and -199 dB, respectively, which is a record among ?0.5 V and <;1 mW oscillatorJ. Du, Y. Hu, T. Siriburanon, and R. B. StaszewskiCICC201910.1109/CICC.2019.8780295https://ieeexplore.ieee.org/document/8780295
A 0.2-V 30-MS/s 11b-ENOB Open-Loop VCO-Based ADC in 28-nm CMOSWe present a 0.2-V open-loop voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) intended for IoT wireless sensor nodes. A resistor-based frequency-tuning scheme helps in mitigating odd-order harmonic distortion induced by the VCO nonlinear transfer characteristic. It also provides a reconfigurable input range, allowing it to exceed the supply by 2.5× (single-ended), and maintaining tolerance against ±10% supply variations. Latch, Hip-Hops, and logic gates within the frequency-to-digital converter are designed for minimum propagation delays, allowing sampling at 30 MS/s. The ADC is implemented in 28-nm CMOS and achieves a peak SNDR of 68 dB, equivalent to an ENOB of 11, over a 61-kHz bandwidth with a 1-Vpp input differential sinewave. It consumes 7 ?W, resulting in a state-of-the-art Walden and Schreier FoM of 27.8 fJ/c-s and 167.4 dB, respectively V. Nguyen, F. Schembari, R. B. Staszewski, SSC-L201910.1109/LSSC.2019.2906777https://ieeexplore.ieee.org/document/8672463
4.48GHz 0.18?m SiGe BiCMOS Exact-Frequency Fractional-N Frequency Synthesizer with Spurious-Tone Suppression Yielding a -80dBc In-Band Fractional SpurThe instantaneous divide value of the multimodulus divider in the feedback path of a fractional-N PLL is determined by a divider controller, which is usually implemented as a digital delta-sigma modulator (D??M). A disadvantage of the fractional-N PLL is the presence of fractional spurs, which result from interaction between the signal introduced by the D??M and nonlinearities in the loop. When fractional spurs at frequencies close to integer boundaries lie inside the loop bandwidth, they cannot be attenuated by filtering. The Successive Requantizer (SR) is an alternative to the D??M-based divider controller, which randomizes the quantization process more effectively than a D??M [1]. Wang et al. reported a worst-case in-band fractional spur of -64dBc in a 2.4GHz charge-pump PLL [1]. Liang and Wang reported a -70dBc worst-case fractional spur in a 2GHz analog PLL with a hybrid VCO and a D??M-based divider controller [2]. Familier and Galton improved the performance of the SR by implementing higher-order noise shaping. They achieved a worst-case fractional spur of -72dBc in a 3.3GHz analog PLL with a third-order SR [3]. The SR quantizes the frequency-control word one bit at a time, and, therefore, requires n stages in the case of an n-bit modulus. Thirunarayanan et al. implemented a hybrid MASH-SR divider-controller structure using four SR quantization blocks [4]. The divider-controller architecture described in this paper enables a 4.48GHz analog PLL to exhibit an in-band fractional spur of -80dBc and a -145dBc reference spur. It comprises a conventional MASH D??M followed by a programmable Probability Mass Redistributor (PMR). The PMR requantizes the output of the D??M and redistributes its samples in such a way that the in-band spurs are reduced by 7dB compared to the D??M aloneM. P. Kennedy, Y. Donnelly, J. Breslin, S. Tulisi, S. Patil, C. Curtin, S. Brookes, B. Shelly, P. Griffin, M. KeaveneyISSCC201910.1109/ISSCC.2019.8662327https://ieeexplore.ieee.org/document/8662327
A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE with PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOSThis paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs directly at 0.5 V, an internal switched-capacitor dc-dc converter “doubles” the supply voltage to all the digital circuitry and particularly regulates the time-to-digital converter (TDC) supply to stabilize its resolution, thus maintaining fixed in-band phase noise (PN) across process, voltage, and temperature (PVT). The ADPLL supports a two-point modulation and forms a Bluetooth low-energy (BLE) transmitter realized in 28-nm CMOS. It maintains in-band PN of -106 dBc/Hz [figure of merit (FoM) of -239.2 dB] and rms jitter of 0.86 ps while dissipating only 1.6 mW at 40-MHz reference. The power consumption reduces to 0.8 mW during the BLE transmission when the DCO switches to open loop.N. Pourmousavian, F.W. Kuo, T. Siriburanon, M. Babaie, R. StaszewskiJSSC)201910.1109/JSSC.2018.2843337https://ieeexplore.ieee.org/document/8396263
Passive SC ?? modulator based on pipelined charge-sharing rotation in 28-nm CMOSIn this paper, we introduce a new switched-capacitor (SC) passive delta-sigma (??) modulator architecture. It is based on a charge-sharing rotation technique, which eliminates any inter-stage loading effects that plague the conventional SC passive ?? modulators. To improve the proposed modulator's noise suppression and stability, an independent extra feedback path and a zeroing stage are added to the 2 nd -stage integrator. Moreover, a pipelining (i.e. interleaving) technique is employed in the passive low-pass filter to relax settling requirements and improve power efficiency. Compared to the ?? modulators with active integrators, the proposed modulator contains only switches, capacitors and one comparator, thus being greatly amenable to nanoscale CMOS process nodes. Implemented in 28-nm CMOS, the proposed ADC occupies a core area of 0.059 mm 2 . It achieves measured SNDR of 81.1 dB and a measured dynamic range (DR) of 83.6 dB with a signal bandwidth of 80 kHz at 40.96 MS/s, while consuming 101.5 ?W. SNDR is maintained above 70 dB across a ±20% supply variation.H. Wang, F. Schembari, and R. B. StaszewskiTCAS-I201910.1109/TCSI.2019.2944467https://ieeexplore.ieee.org/document/8871333
A Generic Foreground Calibration Algorithm For ADCs with Nonlinear Impairmentshis paper presents a generic foreground calibration algorithm which compensates for memoryless nonlinear impairments in pipeline, SAR or hybrid ADC architectures. Amplifier nonlinearity, comparator offsets, capacitance mismatch and settling time errors are considered. During the calibration process, each element of a look up table is computed by mapping each raw ADC output value to an estimate of the corresponding input, and the most likely input corresponding to each raw ADC output is computed and stored in the table; this table is then used during normal operation to map the raw values to the calibrated ADC outputs. Complexity reduction techniques are presented to facilitate an in-circuit hardware implementation in order to reduce foreground calibration time. The algorithm's performance is evaluated using a SAR ADC model suffering from various nonlinear impairments. Results are presented for settling time errors, capacitor mismatch scenarios, and a wide range of nonlinear amplifier parameters, demonstrating a significant performance improvement in all cases.A. Salib; M. F. Flanagan; B. CardiffTCAS-I, 201910.1109/ISCAS.2018.8351187https://ieeexplore.ieee.org/document/8351187
A High-Precision Time Skew Estimation and Correction Technique for Time-Interleaved ADCsThis paper presents an all-digital background calibration technique for the time skew mismatch in time-interleaved ADCs (TIADCs). The technique jointly estimates all of the time skew values by processing the outputs of a bank of correlators. A low-complexity sampling sequence intervention technique, suitable for successive approximation register (SAR) ADC architectures, is proposed to overcome the limitations associated with blind estimation. A two-stage digital correction mechanism based on the Taylor series is proposed to satisfy the target high-precision correction. A quantitative study is performed regarding the requirements imposed on the digital correction circuit in order to satisfy the target performance and yield, and a corresponding filter design method is proposed, which is tailored to meet these requirements. Mitchell's logarithmic multiplier is adopted for the implementation of the principal multipliers in both the estimation and correction mechanisms, leading to a 25% area and power reduction in the estimation circuit. The proposed calibration is synthesized using a TSMC 28-nm HPL process targeting a 2.4-GHz sampling frequency for an eight-sub-ADC system. The calibration block occupies 0.03 mm 2 and consumes 11 mW. The algorithm maintains the SNDR above 65 dB for a sinusoidal input within the target bandwidth.Y. Donnelly; M. P. KennedyTCAS-I, 201910.1109/TCSI.2019.2925181https://ieeexplore.ieee.org/document/8759073
High Order Mismatch Shaping for Low Oversampling RatesDelta Sigma data converters employing high order dynamic element matching (DEM) allow for accurate signal conversion in the presence of DAC mismatch. However, at low oversampling rates, current high order DEM decoders provide little or no improvement in error suppression over lower order designs. In addition, the logic requirement of the DEM decoder increases significantly with each additional DAC bit. This brief presents a high order DEM decoder that improves mismatch shaping performance at low to medium oversampling rates by up to 15 dB, while employing methods to reduce the area overhead of the vector quantizer in the design.V. O’Brien; B. MullaneTCAS-II201910.1109/TCSII.2019.2904180https://ieeexplore.ieee.org/document/8664116
Wandering Spurs in MASH 1-1 Delta-Sigma ModulatorsWandering spurs are a little-studied phenomenon seen in MASH and SQ-digital delta-sigma modulators. They take the form of frequency-modulated spurs which periodically appear in-band. Since modulators are often employed as divide ratio controllers in fractional-N phase lock loops, these spurs can feed into the output phase noise spectrum. In this paper, we explain the mechanism which creates the wandering spurs and offer a prediction for the behavior of these spurs in the MASH 1-1 modulator. Simulation results are presented which confirm our theoretical predictions. Y. Donnelly, M. P. KennedyTCAS-1201910.1109/TCSI.2019.2893435https://ieeexplore.ieee.org/document/8629358
Intuitive understanding of flicker noise reduction via narrowing of conduction angle in voltage-biased oscillatorsThis brief aims to intuitively explain and numerically verify the observed phenomenon of flicker noise reduction in oscillators of reduced conduction angle (i.e., in class-C), which has been presented in literature but never properly explained. The flicker phase noise in a voltage-biased oscillator capable of operating in class-B and class-C is compared and numerically verified using a commercial simulation model of TSMC 28-nm CMOS. We illustrate how narrowing the conduction angle can suppress the 1/f noise up-conversion by decreasing 1/f noise exposure to the asymmetric rising and falling edges of oscillation waveform. The effects of implicit common-mode tank in the class-C operation is also discussed. We further clarify ambiguities among several simulation methods of impulse sensitivity function (ISF) based on periodic small-signal analysis [periodic AC or periodic transfer function (PXF)], which is a key tool in understanding the flicker noise up-conversion. A clearer ISF simulation method based on positive sidebands of PXF is proposed. Y. Hu, T. Siriburanon, and R. B. Staszewski, TCAS-II, 201910.1109/TCSII.2019.2896483https://ieeexplore.ieee.org/document/8630041
Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas RejectionThe digital transmitter (DTX) offers both high power efficiency and frequency flexibility by merging signal amplification and modulation in the switching power amplifier. Yet, the back-end high-speed digital baseband interface is challenging and bulky for obtaining low out-of-band noise. This brief provides an analytical study of the DTX linear interpolation technique, which can be easily utilized for optimizing the replica rejection and noise-filtering capabilities of the DTX.. K-F. Un, F. Zhang, P-I. Mak, R. P. Martins, A. Zhu, R. Bogdan StaszewskiTCAS-II201910.1109/TCSII.2019.2903561https://ieeexplore.ieee.org/document/8662608
Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased OscillatorsThis brief aims to intuitively explain and numerically verify the observed phenomenon of flicker noise reduction in oscillators of reduced conduction angle (i.e., in class-C), which has been presented in literature but never properly explained. The flicker phase noise in a voltage-biased oscillator capable of operating in class-B and class-C is compared and numerically verified using a commercial simulation model of TSMC 28-nm CMOS. We illustrate how narrowing the conduction angle can suppress the 1/f noise up-conversion by decreasing 1/f noise exposure to the asymmetric rising and falling edges of oscillation waveform. The effects of implicit common-mode tank in the class-C operation is also discussed. We further clarify ambiguities among several simulation methods of impulse sensitivity function (ISF) based on periodic small-signal analysis [periodic AC or periodic transfer function (PXF)], which is a key tool in understanding the flicker noise up-conversion. A clearer ISF simulation method based on positive sidebands of PXF is proposed.Y. Hu; T. Siriburanon; R. B. StaszewskiTCAS-II201910.1109/TCSII.2019.2896483https://ieeexplore.ieee.org/document/8630041
Passive SC ?? Modulator Based on Pipelined Charge-Sharing Rotation in 28-nm CMOSIn this paper, we introduce a new switched-capacitor (SC) passive delta-sigma (??) modulator architecture. It is based on a charge-sharing rotation technique, which eliminates any inter-stage loading effects that plague the conventional SC passive ?? modulators. To improve the proposed modulator's noise suppression and stability, an independent extra feedback path and a zeroing stage are added to the 2 nd -stage integrator. Moreover, a pipelining (i.e. interleaving) technique is employed in the passive low-pass filter to relax settling requirements and improve power efficiency. Compared to the ?? modulators with active integrators, the proposed modulator contains only switches, capacitors and one comparator, thus being greatly amenable to nanoscale CMOS process nodes. Implemented in 28-nm CMOS, the proposed ADC occupies a core area of 0.059 mm 2 . It achieves measured SNDR of 81.1 dB and a measured dynamic range (DR) of 83.6 dB with a signal bandwidth of 80 kHz at 40.96 MS/s, while consuming 101.5 ?W. SNDR is maintained above 70 dB across a ±20% supply variationH. Wang, F. Schembari, and R. B. StaszewskiTCAS-I201910.1109/TCSI.2019.2944467https://ieeexplore.ieee.org/document/8871333
A Generic Foreground Calibration Algorithm for ADCs with Nonlinear ImpairmentsThis paper presents a generic foreground calibration algorithm that estimates and corrects memoryless nonlinear impairments in both single channel and time-interleaved analog-to-digital converters (TIADCs), and which is capable of correcting for amplifier nonlinearity, comparator offsets, and capacitance mismatch for each channel. It operates by generating, and then using, a look-up table which maps raw ADC output decision vectors to linearized output. For TIADCs, the algorithm also uses information gained during the calibration phase to estimate timing and gain mismatches among the sub-ADCs. The problem of selecting an appropriate timing reference so as to relax the requirements on the time-skew correction circuitry is statistically analyzed, as is the corresponding impact on manufacturing yield. Accordingly, a new method is proposed having superior performance; for example, in the case of an eight sub-ADC TIADC system, the proposed scheme reduces the time skew correction requirement by 44% compared with conventional methods. The architecture is instrumented with some additional circuitry to facilitate built-in self-test, allowing manufacturing test time and cost reductions. Implementation aspects are discussed, and several complexity reduction techniques are presented along with synthesis results from a Verilog implementation of the calibration engine.A. Salib; M. F. Flanagan; B. Cardiff, TCAS-I201910.1109/TCSI.2018.2870529https://ieeexplore.ieee.org/document/8490116
A High-Precision Time Skew Estimation and Correction Technique for Time-Interleaved ADCsThis paper presents an all-digital background calibration technique for the time skew mismatch in time-interleaved ADCs (TIADCs). The technique jointly estimates all of the time skew values by processing the outputs of a bank of correlators. A low-complexity sampling sequence intervention technique, suitable for successive approximation register (SAR) ADC architectures, is proposed to overcome the limitations associated with blind estimation. A two-stage digital correction mechanism based on the Taylor series is proposed to satisfy the target high-precision correction. A quantitative study is performed regarding the requirements imposed on the digital correction circuit in order to satisfy the target performance and yield, and a corresponding filter design method is proposed, which is tailored to meet these requirements. Mitchell's logarithmic multiplier is adopted for the implementation of the principal multipliers in both the estimation and correction mechanisms, leading to a 25% area and power reduction in the estimation circuit. The proposed calibration is synthesized using a TSMC 28-nm HPL process targeting a 2.4-GHz sampling frequency for an eight-sub-ADC system. The calibration block occupies 0.03 mm 2 and consumes 11 mW. The algorithm maintains the SNDR above 65 dB for a sinusoidal input within the target bandwidth. A. Salib; M. F. Flanagan; B. Cardiff, TCAS-I201910.1109/TCSI.2019.2915282https://ieeexplore.ieee.org/document/8725937
Prediction of Phase Noise and Spurs in a Nonlinear Fractional-N Frequency SynthesizerInteger boundary spurs appear in the passband of the loop response of fractional-N phase lock loops and are, therefore, a potentially significant component of the phase noise. In spite of measures guaranteeing spur-free modulator outputs, the interaction of the modulation noise from a divider controller with inevitable loop nonlinearities produces such spurs. This paper presents analytical predictions of the locations and amplitudes of the spurs and accompanying noise floor levels produced by interaction between a divider controller output and a PLL loop with a static nonlinearity. A key finding is that the spur locations and amplitudes can be estimated by using only the knowledge of the structure and pdf of the accumulated modulator noise and the nonlinearity. These predictions also offer new insights into why the spurs appeaY. Donnelly; M. P. KennedyTCAS-I201910.1109/TCSI.2019.2925181https://ieeexplore.ieee.org/document/8759073
High Order Mismatch Shaping for Low Oversampling RatesDelta Sigma data converters employing high order dynamic element matching (DEM) allow for accurate signal conversion in the presence of DAC mismatch. However, at low oversampling rates, current high order DEM decoders provide little or no improvement in error suppression over lower order designs. In addition, the logic requirement of the DEM decoder increases significantly with each additional DAC bit. This brief presents a high order DEM decoder that improves mismatch shaping performance at low to medium oversampling rates by up to 15 dB, while employing methods to reduce the area overhead of the vector quantizer in the design.V. O’Brien; B. MullaneTCAS-II201910.1109/TCSII.2019.2904180https://ieeexplore.ieee.org/document/8664116
Wandering Spurs in MASH 1-1 Delta-Sigma ModulatorsWandering spurs are a little-studied phenomenon seen in MASH and SQ-digital delta-sigma modulators. They take the form of frequency-modulated spurs which periodically appear in-band. Since modulators are often employed as divide ratio controllers in fractional-N phase lock loops, these spurs can feed into the output phase noise spectrum. In this paper, we explain the mechanism which creates the wandering spurs and offer a prediction for the behavior of these spurs in the MASH 1-1 modulator. Simulation results are presented which confirm our theoretical predictions.Y. Donnelly, M. P. Kennedy, TCAS-I, 201910.1109/TCSI.2019.2893435https://ieeexplore.ieee.org/document/8629358
Intuitive understanding of flicker noise reduction via narrowing of conduction angle in voltage-biased oscillatorsThis brief aims to intuitively explain and numerically verify the observed phenomenon of flicker noise reduction in oscillators of reduced conduction angle (i.e., in class-C), which has been presented in literature but never properly explained. The flicker phase noise in a voltage-biased oscillator capable of operating in class-B and class-C is compared and numerically verified using a commercial simulation model of TSMC 28-nm CMOS. We illustrate how narrowing the conduction angle can suppress the 1/f noise up-conversion by decreasing 1/f noise exposure to the asymmetric rising and falling edges of oscillation waveform. The effects of implicit common-mode tank in the class-C operation is also discussed. We further clarify ambiguities among several simulation methods of impulse sensitivity function (ISF) based on periodic small-signal analysis [periodic AC or periodic transfer function (PXF)], which is a key tool in understanding the flicker noise up-conversion. A clearer ISF simulation method based on positive sidebands of PXF is proposed. Y. Hu, T. Siriburanon, and R. B. StaszewskiTCAS-II201910.1109/TCSII.2019.2896483https://ieeexplore.ieee.org/document/8630041
Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas RejectionThe digital transmitter (DTX) offers both high power efficiency and frequency flexibility by merging signal amplification and modulation in the switching power amplifier. Yet, the back-end high-speed digital baseband interface is challenging and bulky for obtaining low out-of-band noise. This brief provides an analytical study of the DTX linear interpolation technique, which can be easily utilized for optimizing the replica rejection and noise-filtering capabilities of the DTX.K-F. Un, F. Zhang, P-I. Mak, R. P. Martins, A. Zhu, R. Bogdan StaszewskiTCAS-II201910.1109/TCSII.2019.2903561https://ieeexplore.ieee.org/document/8662608
Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased OscillatorsThis brief aims to intuitively explain and numerically verify the observed phenomenon of flicker noise reduction in oscillators of reduced conduction angle (i.e., in class-C), which has been presented in literature but never properly explained. The flicker phase noise in a voltage-biased oscillator capable of operating in class-B and class-C is compared and numerically verified using a commercial simulation model of TSMC 28-nm CMOS. We illustrate how narrowing the conduction angle can suppress the 1/f noise up-conversion by decreasing 1/f noise exposure to the asymmetric rising and falling edges of oscillation waveform. The effects of implicit common-mode tank in the class-C operation is also discussed. We further clarify ambiguities among several simulation methods of impulse sensitivity function (ISF) based on periodic small-signal analysis [periodic AC or periodic transfer function (PXF)], which is a key tool in understanding the flicker noise up-conversion. A clearer ISF simulation method based on positive sidebands of PXF is proposed.Y. Hu; T. Siriburanon; R. B. StaszewskiTCAS-II201910.1109/TCSII.2019.2896483https://ieeexplore.ieee.org/document/8630041
An Adaptive-Resolution Quasi-Level-Crossing-Sampling ADC Based on Residue Quantization in 28-nm CMOSWe present a digitally intensive adaptive-resolution (AR) quasi-level-crossing-sampling (quasi-LCS) analog-to-digital converter (ADC) for Internet-of-Things wireless networks, where the power consumed in data transmission, processing, and storage can be significantly reduced by minimizing the ADC's gross output bit-rate. The AR quasiLCS ADC is implemented as a delta-modulator and adopts a 4-bit asynchronous SAR ADC to quantize the residue voltage signal, thus allowing a straightforward implementation of LCS and AR algorithms in the digital domain, as well as yielding a digital-friendly architecture. Fabricated in 28-nm CMOS, this ADC achieves an SNDR of 53dB over 1.42 MHz signal bandwidth while consuming 205 ?W and an active area of 0.0126 mm 2H. Wang, F. Schembari, M. Mi?kowicz, R.B. Staszewski201910.1109/LSSC.2019.2899723https://ieeexplore.ieee.org/document/8642805
A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return PathThis paper presents a millimeter-wave (mmW) frequency generation stage aimed at minimizing phase noise (PN) via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A 2nd-harmonic resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for explicit common-mode current return path. Class-F operation with 3rd-harmonic boosting and extraction techniques allow maintaining high quality factor of a 10-GHz tank at the 30-GHz frequency generation. We further propose a comprehensive quantitative analysis method of flicker noise upconversion mechanism exploiting latest insights into the flicker noise mechanisms in nanoscale short-channel transistors, and it is numerically verified against foundry models. The proposed 27.3to 31.2-GHz oscillator is implemented in TSMC 28-nm CMOS. It achieves PN of -106 dBc/Hz at 1-MHz offset and figure-of-merit (FoM) of -184 dBc/Hz at 27.3 GHz. Its flicker phase-noise (1/f 3 ) corner of 120 kHz is an order-of-magnitude better than currently achievable at mmW. Y. Hu, T. Siriburanon, R. StaszewskiJSSC)201810.1109/JSSC.2018.2818681https://ieeexplore.ieee.org/document/8345650
Instantaneous Sample Indexed Magnitude-Selective Affine Function-Based Behavioral Model for Digital Predistortion of RF Power Amplifiers
In this paper, we present a new behavioral model for digital predistortion (DPD) of RF power amplifiers in wireless transmitters. Derived from the decomposed vector rotation model, the new model uses magnitude-selective affine functions as nonlinear operators to construct nonlinear behavior of the model, leading to a highly efficient hardware implementation. Moreover, cross-terms are carefully redesigned based on a new formulation of model structure that not only improves the modeling performance but also significantly lowers the complexity of model extraction. Simulation and experimental results have demonstrated its superior performance and efficient hardware implementation, making this model well suitable for future DPD deployment in 5G small cell base stations where digital hardware resource is highly constrained.Y. Li ; W. Cao ; A. Zhu, (MTT), 201810.1109/TMTT.2018.2855134https://ieeexplore.ieee.org/document/8438993
Behavioral Modeling of SAR ADCs in SimulinkThis paper presents a toolbox for the behavioral simulation of SAR ADCs in Simulink®. The models include the most limiting circuit effects such as sampled thermal noise, capacitor mismatch, finite settling, comparator noise and offset. A user friendly interface is also included to allow study and high-level design of SAR ADCs, which is illustrated by means of a design example. It is also shown that the proposed toolbox is several orders of magnitude faster than electrical simulators, while keeping a high accuracy.26. S. Asghar, S. Afridi, A. Pillai, A. Schuler, J. M. de la Rosa, I. O’Connell, (ISCAS) 201810.1109/ISCAS.2018.8351056https://ieeexplore.ieee.org/document/8351056
High-Speed Nested Cascaded MASH Digital Delta-Sigma Modulator-Based Divider Controller.The MASH Digital Delta-Sigma Modulator (DDSM) based divider controller represents a speed bottleneck in state of the art commercial PLL-based fractional-N frequency synthesizers. As next generation systems require higher phase detector frequencies, there is a need to make ever faster divider controllers. This paper describes a fine-grained nested cascaded MASH DDSM which is significantly faster than state of the art divider controllers, thereby eliminating the current speed bottleneck.Y. Donnelly, H. Mo and M.P. KennedyISCAS201810.1109/ISCAS.2018.8351624https://ieeexplore.ieee.org/document/8351624
A 2MS/S, 11.22 ENOB, 3.2 Vpp-D SAR ADC with Improved DNL and Offset Calculation”, IEEE International Symposium on Circuits and Systems, S. Asghar, S. Afridi, A. Pillai, A. Schuler, J. M. de la Rosa, I. O’Connell, ISCAS)2018
A Generic Foreground Calibration Algorithm for ADCs with Nonlinear Impairments”This paper presents a generic foreground calibration algorithm which compensates for memoryless nonlinear impairments in pipeline, SAR or hybrid ADC architectures. Amplifier nonlinearity, comparator offsets, capacitance mismatch and settling time errors are considered. During the calibration process, each element of a look up table is computed by mapping each raw ADC output value to an estimate of the corresponding input, and the most likely input corresponding to each raw ADC output is computed and stored in the table; this table is then used during normal operation to map the raw values to the calibrated ADC outputs. Complexity reduction techniques are presented to facilitate an in-circuit hardware implementation in order to reduce foreground calibration time. The algorithm's performance is evaluated using a SAR ADC model suffering from various nonlinear impairments. Results are presented for settling time errors, capacitor mismatch scenarios, and a wide range of nonlinear amplifier parameters, demonstrating a significant performance improvement in all cases.28. A. Salib; M. F. Flanagan; B. CardiffISCAS201810.1109/ISCAS.2018.8351187https://ieeexplore.ieee.org/document/8351187
An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ?? Loop,To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order ?? time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A system self-calibration algorithm is proposed to calibrate nonlinearities of the analog circuitry. The operation is robust over PVT variations since the delay information is normalized to the input clock period. To verify the proposed idea, two different digital-to-time converters performing the on-chip delay are measured and analyzed at 50-MHz clocking frequency with 0.65-ps standard time deviation per measurement.P. Chen, X. Huang, Y. Chen, L. Wu, R. Staszewski. TCAS-I201810.1109/TCSI.2018.2857999https://ieeexplore.ieee.org/document/8436438
A Design Method for a Nested MASH-SQ Hybrid Divider Controller for Fractional-N Frequency SynthesizersFractional-N frequency synthesizers contain a divider controller which implements the fractional division. The interaction between the quantization noise from the divider controller and nonlinearities within the synthesizer will cause undesirable degradation of the output phase noise performance. The most common divider controller architecture is the Multi-stAge noiSe sHaping Digital Delta-Sigma Modulator (MASH DDSM). Because the MASH DDSM suffers from performance degradation in the presence of nonlinearities, Galton et al. introduced a new divider controller architecture called the Successive reQuantizer (SQ). The SQ is designed to eliminate spurious tones caused by polynomial nonlinearities of a given order. A drawback of the SQ is that its hardware consumption is significantly higher than that of a MASH DDSM. A nested MASH-SQ hybrid has been introduced to achieve similar spectral performance to the SQ but with reduced hardware cost. In this paper, we present a design method for a nested MASH-SQ hybrid divider controller for fractional-N frequency synthesizers.D. Mai and M.P. Kennedy.TCAS-I, 201810.1109/TCSI.2018.2816939https://ieeexplore.ieee.org/document/8333801
Techniques for reducing ULP device power consumptionIndustry Session 5: Energy HarvestingO’Connell, I, and O’Riordan, APEC2018
A 33-GHz LNA for 5G Wireless Systems in 28-nm Bulk CMOSThis brief presents a design procedure of a compact 33-GHz low-noise amplifier (LNA) for fifth generation (5G) applications realized in 28-nm LP CMOS. Based on the unique set of challenges presented by advanced nanoscale CMOS, the emphasis is put here on the optimization of design and layout techniques for active and passive components in the presence of rigorous metal density rules and other back-end-of-the-line challenges. All passive components are designed and optimized with full-wave electromagnetic simulations for a high quality factor. In addition, layout techniques help to miniaturize the total area as the suggested 5G frequency band of 33 GHz is not high enough to provide a sufficiently compact chip size. The resulting increase in the concentration of required metal fills furthermore makes this optimization more challenging. The fabricated LNA consists of two cascode stages with a total core area of 0.68×0.34 mm 2 . It exhibits 4.9-dB noise figure and 18.6-dB gain at 33 GHz while consuming only 9.7 mW from a 1.2-V power supply.M. Keshavarz Hedayati; A. Abdipour; R. Sarraf Shirazi; C. Cetintepe; R. B. StaszewskiTCAS-II201810.1109/TCSII.2018.2859187https://ieeexplore.ieee.org/document/8418759
A Design Method for a Nested MASH-SQ Hybrid Divider Controller for Fractional-N Frequency SynthesizersFractional-N frequency synthesizers contain a divider controller which implements the fractional division. The interaction between the quantization noise from the divider controller and nonlinearities within the synthesizer will cause undesirable degradation of the output phase noise performance. The most common divider controller architecture is the Multi-stAge noiSe sHaping Digital Delta-Sigma Modulator (MASH DDSM). Because the MASH DDSM suffers from performance degradation in the presence of nonlinearities, Galton et al. introduced a new divider controller architecture called the Successive reQuantizer (SQ). The SQ is designed to eliminate spurious tones caused by polynomial nonlinearities of a given order. A drawback of the SQ is that its hardware consumption is significantly higher than that of a MASH DDSM. A nested MASH-SQ hybrid has been introduced to achieve similar spectral performance to the SQ but with reduced hardware cost. In this paper, we present a design method for a nested MASH-SQ hybrid divider controller for fractional-N frequency synthesizers.D. Mai and M.P. KennedyTCAS-I201810.1109/TCSI.2018.2816939https://ieeexplore.ieee.org/document/8333801
Observations and Analysis of Wandering Spurs in MASH-Based Fractional-N Frequency SynthesizersFractional-N frequency synthesizers can exhibit a phenomenon known as wandering spurs. This brief traces the root cause of the phenomenon to the divider controller. Predictions of the repeat period and the wander rate in the case of a multi-stage noise shaping delta-sigma modulator (MASH DDSM)-based divider controller are given. Simulations, based on CppSim simulations of a type-II CP-PLL with a third-order digital delta-sigma based divider controller, confirm the theoretical predictions.D. Mai, H. Mo, M.P. KennedyTCAS-II201810.1109/TCSII.2018.2821636https://ieeexplore.ieee.org/document/8328872
Digital Suppression of Transmitter Leakage in FDD RF Transceivers: Aliasing Elimination and Model SelectionThe transmitter (TX)-induced interference due to power amplifier nonlinearities poses severe desensitization problems to the receiver chain in frequency-division duplexing transceivers. Due to nonlinear signal process involved, a high sampling rate is normally required in the existing digital suppression approaches, which can result in high cost and high power consumption in wideband systems. In this paper, a new digital suppression model is proposed to cancel the TX leakage at baseband with a low sampling rate. The cancellation model is based on the modified decomposed vector rotation model. With the addition of cross-term products, the enhanced model is capable of eliminating the aliasing effect arising from the reduced sampling rate. Theoretical analysis of aliasing elimination is presented, and the algorithm is subsequently verified by both simulation and experiment results, confirming the effectiveness and feasibility of the proposed cancellation technique for TX leakage suppression. Compared with conventional solutions, the new approach uses much less hardware resource and consumes much lower power while achieving comparable performance.29. W. Cao, Y. Li, and A. Zhu, MTT201710.1109/TMTT.2017.2772789https://ieeexplore.ieee.org/document/8169681
Direct Error-Searching SPSA Based Model Extraction for Digital Predistortion of RF Power Amplifiers'This paper presents a low-complexity architecture to extract model coefficients for digital predistortion of radio frequency power amplifiers. The proposed approach directly updates the model coefficients online using a stochastic optimization algorithm that utilizes random perturbation of the model coefficients to determine the coefficient updating direction and converge toward the optimum solution. This technique avoids resource-intensive matrix operations and the requirement for an offline error model in the conventional model extraction techniques and thus drastically reduces the implementation complexity. The complete model extraction solution has been implemented on a field-programmable gate array, and it is shown that the hardware resource usage is remarkably low. Experimental measurements were conducted on a gallium nitride Doherty amplifier excited by Long Term Evolution signals and the results showed that the proposed technique can achieve linearization performance comparable to that obtained by using the conventional and significantly more complex solutions.30. Kelly, N. and Zhu, A. MTT201710.1109/TMTT.2017.2748128https://ieeexplore.ieee.org/document/8068938
1-bit Observation for Direct-Learning-Based Digital Predistortion of RF Power AmplifiersIn this paper, we propose a low-cost data-acquisition approach for model extraction of digital predistortion (DPD) of RF power amplifiers. The proposed approach utilizes only 1-bit-resolution analog-to-digital converters (ADCs) in the observation path to digitize the error signal between the input and output signals. The DPD coefficients are then estimated based on the direct learning architecture using the measured signs of the error signal. The proposed solution is proved feasible in theory, and the experimental results show that the proposed algorithm achieves the performance equivalent to that using the conventional method. Replacing high-resolution ADCs with 1-bit comparators in the feedback path can dramatically reduce the power consumption and cost of the DPD system. The 1-bit solution also makes DPD become practically implementable in future broadband systems since it is relatively straightforward to achieve an ultrahigh sampling speed in data conversion using only simple comparators.31. Wang, H., Li, G., Zhou, C., Tao, W., Liu, F., and Zhu, A. MTT201710.1109/TMTT.2016.2642945https://ieeexplore.ieee.org/document/7829260
Magnitude-Selective Affine Function Based Digital Predistorter for RF Power Amplifiers in 5G Small-Cell TransmittersTo accommodate small-cell deployment in future 5G wireless communications, a magnitude-selective affine function based digital predistortion model for RF power amplifiers is proposed. This model has a very simple model structure and is easy to implement. Experimental results showed, by employing this model, substantial hardware resource reduction can be achieved without sacrificing performance in comparison with the existing models.33. Cao, W., Li, Y., and Zhu, AMTT201710.1109/MWSYM.2017.8058921https://ieeexplore.ieee.org/document/8058921
A 30-GHz Class-F23 Oscillator in 28nm CMOS Using Harmonic Extraction and Achieving 120 kHz 1?f 3 CornerThis paper presents a mmW frequency generation stage aimed at minimizing phase noise via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A second-harmonic tank resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for shortest and well controlled common-mode current return path. Class-F operation with third-harmonic boosting and extraction techniques allow maintaining high quality factor of a 10 GHz tank at the 30 GHz frequency generation while providing implicit divide-by-3 functionality. The proposed 27.3-31.2 GHz oscillator is implemented in 28-nm CMOS. It achieves phase noise of -106 dBc/Hz at 1-MHz offset and figure-of-merit (FoM) of -184 dB at 27.3GHz. Its flicker phase-noise (1/f 3 ) corner of 120 kHz is an order-of-magnitude better than currently achievable at mmW Y. Hu, T. Siriburanon, R. StaszewskiESSCIRC201710.1109/ESSCIRC.2017.8094532https://ieeexplore.ieee.org/document/8094532
A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOSThis paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs directly at 0.5 V, an internal switched-capacitor dc-dc converter “doubles” the supply voltage to all the digital circuitry and particularly regulates the time-to-digital converter (TDC) supply to stabilize its resolution, thus maintaining fixed in-band phase noise (PN) across process, voltage, and temperature (PVT). The ADPLL supports a two-point modulation and forms a Bluetooth low-energy (BLE) transmitter realized in 28-nm CMOS. It maintains in-band PN of -106 dBc/Hz [figure of merit (FoM) of -239.2 dB] and rms jitter of 0.86 ps while dissipating only 1.6 mW at 40-MHz reference. The power consumption reduces to 0.8 mW during the BLE transmission when the DCO switches to open loop F. W. Kuo, N. Pourmousavian, T. Siriburanon, R. StaszewskiIEEE Symposium on VLSI Circuits201710.1109/JSSC.2018.2843337https://ieeexplore.ieee.org/document/8396263
A low-complexity correlation-based time skew estimation technique for time-interleaved SAR ADCsThis paper presents a technique to estimate the time skew in time-interleaved ADCs. The proposed method estimates all of the time skew parameters jointly based on observations from a bank of correlators. The proposed method works for an arbitrary number of sub-ADCs. For implementation of the correlator bank, we propose the use of Mitchell's logarithmic multiplier and a hardware reuse mechanism, thereby reducing the complexity and power consumption. Also, we explain why blind estimation techniques alone (including the proposed one) are not always sufficient for time skew estimation for certain classes of input signal; for the proposed approach, however, a simple modification to the analogue circuit (suitable for SAR ADCs) is shown to successfully deal with such problems, with only a minor penalty in power and area. The technique is verified by extensive simulations including a spectrally rich input signal in which an MTPR (multi-tone power ratio) improvement from 29dB to 62dB was achieved for a TIADC system having 16 sub-ADCsA. Salib, B. Cardiff, M. F. FlanaganISCAS201710.1109/ISCAS.2017.8050309https://ieeexplore.ieee.org/document/8050309
Nonlinearity-induced spurious tones and noise in digitally-assisted frequency synthesizersFrequency synthesizers based on finite state machines are notorious for producing spurious tones (spurs). These spurs can be inherent in the architecture or may result from interactions between quantization noise and nonlinearities. This paper presents recent results, including descriptions of the problems and emerging solutions thereto. M.P. Kennedy, H. Mo and D. MaiISCAS201710.1109/ISCAS.2017.8050553https://ieeexplore.ieee.org/document/8050553
Masked Dithering of MASH Digital Delta-Sigma Modulators with Constant Inputs using Multiple Linear Feedback Shift RegistersThe output signal of a digital delta-sigma modulator (DDSM) with a constant input may has a small fundamental period and therefore its spectrum may be characterized by a small number of strong periodic tones. Pseudorandom dither can be used to break up the tones, but it is indistinguishable from signal. The dither signal can be masked by using short sequence lengths but this may result in ineffective dithering and consequent tonal behavior. This paper shows how to use multiple shaped dither signals which are masked by the shaped quantization noise of the DDSM and yield a long fundamental output periodH. Mo and M.P. KennedyTCAS-I201710.1109/TCSI.2017.2670365https://ieeexplore.ieee.org/document/7870665
Influence of Initial Conditions on the Fundamental Periods of LFSR-Dithered MASH Digital Delta-Sigma Modulators with Constant InputsA digital delta-sigma modulator (DDSM) with a constant input may produce a periodic output with a small fundamental period, resulting in strong tonal output behavior instead of the expected shaped white quantization noise. In practice, the problem is alleviated by dithering the DDSM. Pseudorandom dither generators based on linear feedback shift registers (LFSRs) are widely used to “break up” periodic cycles in DDSMs with constant inputs. Pseudorandom dither signals are themselves periodic and can lead to relatively short output sequences from dithered DDSMs. It is known that the fundamental period of the output signal depends not only on the input and the initial condition of the DDSM but also on the initial state of the LFSR. This brief shows that bad LFSR initial conditions can lead to ineffective dithering, producing short cycles and strong tonal behavior. Furthermore, it explains how to set the initial state of the DDSM as a function of the initial state of the LFSR in order to obtain a maximum-length dithered output.H. Mo and M.P. Kennedy. TCAS-II,201710.1109/TCSII.2016.2567480https://ieeexplore.ieee.org/document/7469364
A Broadband High-Efficiency Doherty Power Amplifier with Integrated Compensating ReactanceThis paper presents a high-efficiency gallium nitride Doherty power amplifier (DPA) using an integrated compensating reactance (CR) for broadband operation. With an additional quarter-wavelength transmission line integrated in the peaking amplifier output, a CR is generated to compensate the load impedance of the carrier amplifier in the low-power region and thus enhance the back-off efficiency over a wide frequency range without affecting the Doherty load modulation at saturation. For this purpose, a peaking output matching network (OMN) is employed to convert the output impedance of the peaking device into quasi-short circuit when it is off and achieve proper impedance matching when it is on. A two-point matching technique using the transmission (ABCD) matrix is employed to design such desired OMN. Measurement results show that the DPA has a 6-dB back-off efficiency of 50%-55% and a saturated efficiency of 57%-71% over the frequency band of 1.7-2.8 GHz (49% fractional bandwidth). When driven by a 20-MHz long term evolution modulated signal at 6.5-dB back-off power, the DPA can achieve an average efficiency of more than 50% with high linearity after linearization over the design frequency band.Xia, J., Yang, M., Guo, Y., and Zhu, AMTT201610.1109/TMTT.2016.2574861https://ieeexplore.ieee.org/document/7488227
Highly Efficient Broadband Continuous Inverse Class-F Power Amplifier Design Using Modified Elliptic Low-Pass Filtering Matching NetworkThis paper proposes a design approach for a broadband and high-efficiency continuous inverse Class-F (CCF-1) power amplifier (PA) based on a modified elliptic low-pass filtering (LPF) matching network (MN). From theoretical and practical perspectives, the importance of a swift impedance transition from the higher end of the fundamental frequency band to the lower end of the second harmonic band is discussed, when designing a broadband single-mode PA. After being compared with widely used Chebyshev LPF MNs, a modified elliptic LPF MN, which provides a sharp roll-off, is utilized to provide the required rapid transition. A step-by-step design procedure of the proposed modified elliptic LPF MN is presented. Experimental results show that a high-efficiency CCF -1 PA is realized from 1.35 to 2.5 GHz (fractional bandwidth = 60%) with measured drain efficiency of 68%-82% and output power of 41.1-42.5 dBm. When stimulated by a 20-MHz LTE signal with an average output power of approximately 34.5 dBm, the proposed PA, combined with digital pre-distortion, achieved adjacent channel leakage ratios (ACLRs) below -45 dBc, with average efficiency (AE) ranging from 37% to 45.8%. Similar performance is measured when the proposed PA is driven by a dual-band dual-mode modulated signal with a 100-MHz instantaneous bandwidth at a center frequency of 2.14 GHz.Yang, M., Xia, J., Guo, Y., and Zhu, AMTT201610.1109/TMTT.2016.2544318https://ieeexplore.ieee.org/document/7445243
Low Complexity Stochastic Optimization-Based Model Extraction for Digital Predistortion of RF Power AmplifiersThis paper introduces a low-complexity stochastic optimization-based model coefficients extraction solution for digital predistortion of RF power amplifiers (PAs). The proposed approach uses a closed-loop extraction architecture and replaces conventional least squares (LS) training with a modified version of the simultaneous perturbation stochastic approximation (SPSA) algorithm that requires a very low number of numerical operations per iteration, leading to considerable reduction in hardware implementation complexity. Experimental results show that the complete closed-loop stochastic optimization-based coefficient extraction solution achieves excellent linearization accuracy while avoiding the complex matrix operations associated with conventional LS techniques.Kelly, N., and Zhu, A. MTT201610.1109/TMTT.2016.2547383https://ieeexplore.ieee.org/document/7451269
A channelized sideband distortion model for suppressing unwanted emission of Q-band millimeter wave transmittersIn this paper, a channelized sideband distortion model is proposed to suppress the unwanted emission of Q-band millimeter wave (mmWave) transmitters in wideband contiguous carrier aggregation scenarios. By employing this model, the compensating bandwidth or center frequency can be agilely controlled. Experiments were conducted on a 40 GHz mmWave power amplifier to validate this idea. The satisfactory performance proved that the proposed model is a promising candidate for future 5G applications.Yu, C., Sun, H., Zhu, X., Hong, W., and Zhu, AInternational Microwave Symposium201610.1109/MWSYM.2016.7540308https://ieeexplore.ieee.org/document/7540308
A method to quantify the dependence of spur heights on offset current in a CP-PLLThis paper presents a computationally efficient method to determine how the pattern of spurs in a fractional-N frequency synthesizer depends on the local nonlinearity of the phase-frequency detector and charge pump (PFD-CP). It also presents a case study using a transistor-level model of a common PFD-CP architectureM.P. Kennedy, H. Mo, Z. Huang and J.P. Lana. ISCAS201610.1109/ISCAS.2016.7538885https://ieeexplore.ieee.org/document/7538885
Comparative analysis of differential colpitts and cross-coupled VCOs in 180 nm Si-Ge HBT technologyIt has been shown in the literature that a cross-coupled CMOS LC VCO will outperform an equivalent Colpitts VCO. In the case of bipolar devices, the jury is still out. This paper reports a comparative analysis of phase noise (PN), tuning range (TR), dissipated DC power and Figure of Merit (FoM) in cross-coupled and differential Colpitts LC VCOs topologies designed in 180 nm Si-Ge HBT technology for operation around 5 GHz. SpectreRF simulations show that the cross-coupled topology exhibits a minimum PN equal to -108 dBc/Hz, a tuning range of 17.5% and a dissipated DC power of 12.6 mW, with a FoM equal to 204 dB, while the Colpitts topology exhibits a minimum PN over the tuning range equal to -113 dBc/Hz, a tuning range of 21.6% and a dissipated DC power of 14.1 mW, with a FoM equal to 212 dB. This suggests that, for the considered technology, the differential Colpitts can exhibit better overall performance than the cross-coupled VCO.V. Marotta, G. Macera, M.P. Kennedy and E. NapoliISCAS201610.1109/ISCAS.2016.7538883https://ieeexplore.ieee.org/abstract/document/7538883
Comparison of analytical predictions of the noise floor due to static charge pump mismatch in fractional-N frequency synthesizersInteraction between the requantizer's periodic output and charge pump mismatch nonlinearity in a fractional-N frequency synthesizer causes it to exhibit an elevated inband noise floor and spurs. In this paper, we consider three leading analytical predictions from the literature. By comparing simulation results with analytical predictions, we show that the two most common approaches fail to deal correctly with offsets, while the method based on Price's theorem works well. H. Mo, G. Hu and M.P. KennedyISCAS201610.1109/ISCAS.2016.7539077https://ieeexplore.ieee.org/document/7539077
Masked Dithering of MASH Digital Delta-Sigma Modulators with Constant Inputs using Linear Feedback Shift RegistersThe output signal of a digital delta-sigma modulator (DDSM) with a constant input may has a small fundamental period and therefore its spectrum may be characterized by a small number of strong periodic tones. Pseudorandom dither can be used to break up the tones, but it is indistinguishable from signal. The dither signal can be masked by using short sequence lengths but this may result in ineffective dithering and consequent tonal behavior. This paper shows how to use multiple shaped dither signals which are masked by the shaped quantization noise of the DDSM and yield a long fundamental output periodH. Mo and M.P. KennedyTCAS-I, 201610.1109/TCSI.2017.2670365https://ieeexplore.ieee.org/document/7870665
Analog Assisted Multichannel Digital Postcorrection for Time-Interleaved ADCsThis brief introduces a new digital postcorrection technique for calibrating time-interleaved analog-to-digital converters (ADCs). It utilizes one additional sub-ADC to resolve the performance degradation problem near the Nyquist rate that occurred in the conventional multichannel filtering approach. Time skew, gain, offset, and bandwidth mismatches as well as the sub-ADC nonlinearities are all included in the proposed model. One group of coefficients extracted in foreground can be applied to any input frequencies in normal operation. An additional analog subcircuit path is required, but the digital part of the implementation becomes much simpler, which ensures that the overall system complexity does not increase. Furthermore, the digital correction structure can reuse the hardware units in a time-multiplexing manner for further power and resource savings. A 12-b four-channel 1-GS/s ADC is used to demonstrate the performance of the proposed postcorrection.Huang, G., Yu, C., and Zhu, ATCAS-II .201610.1109/TCSII.2016.2530899https://ieeexplore.ieee.org/document/7410046
Influence of Initial Conditions on the Fundamental Periods of LFSR-Dithered MASH Digital Delta-Sigma Modulators with Constant InputsA digital delta-sigma modulator (DDSM) with a constant input may produce a periodic output with a small fundamental period, resulting in strong tonal output behavior instead of the expected shaped white quantization noise. In practice, the problem is alleviated by dithering the DDSM. Pseudorandom dither generators based on linear feedback shift registers (LFSRs) are widely used to “break up” periodic cycles in DDSMs with constant inputs. Pseudorandom dither signals are themselves periodic and can lead to relatively short output sequences from dithered DDSMs. It is known that the fundamental period of the output signal depends not only on the input and the initial condition of the DDSM but also on the initial state of the LFSR. This brief shows that bad LFSR initial conditions can lead to ineffective dithering, producing short cycles and strong tonal behavior. Furthermore, it explains how to set the initial state of the DDSM as a function of the initial state of the LFSR in order to obtain a maximum-length dithered output.H. Mo and M.P. KennedyTCAS-II201610.1109/TCSII.2016.2567480https://ieeexplore.ieee.org/document/7469364
Analog Assisted Multichannel Digital Postcorrection for Time-Interleaved ADCsThis brief introduces a new digital postcorrection technique for calibrating time-interleaved analog-to-digital converters (ADCs). It utilizes one additional sub-ADC to resolve the performance degradation problem near the Nyquist rate that occurred in the conventional multichannel filtering approach. Time skew, gain, offset, and bandwidth mismatches as well as the sub-ADC nonlinearities are all included in the proposed model. One group of coefficients extracted in foreground can be applied to any input frequencies in normal operation. An additional analog subcircuit path is required, but the digital part of the implementation becomes much simpler, which ensures that the overall system complexity does not increase. Furthermore, the digital correction structure can reuse the hardware units in a time-multiplexing manner for further power and resource savings. A 12-b four-channel 1-GS/s ADC is used to demonstrate the performance of the proposed postcorrection.Huang, G., Yu, C., and Zhu, ATCAS-II, 201610.1109/TCSII.2016.2530899https://ieeexplore.ieee.org/document/7410046
Design of a Sample-and-Hold Analog Front End for a 56Gb/s PAM-4 Receiver Using 65nm CMOSWe 1 present an analog front end for a PAM-4 clock and data recovery circuit designed in 65nm CMOS. The front end consists of an arrangement of 8 interleaved master and slave sample-and-hold circuits, to be followed by an array of dynamic comparators. Each interleaved channel contains two wideband buffers with accurate bias and common-mode control circuitry to drive the sample-and-hold circuits. The worst-case (across process, temperature and supply voltage corners) aperture time of the sampling front end is 17ps for a differential input voltage swing of 200mV, sufficient to resolve a 56Gb/s (28Gbaud) PAM-4 signal. The power consumption is 55mW from 1.0V and 1.2V supply voltagesK. Sadeghipour et alICAS201510.1109/ISCAS.2015.7168956https://ieeexplore.ieee.org/document/7168956
A 78.8-92.8 GHz 4-bit 0-360º Active Phase Shifter in 28nm FDSOI CMOS with 2.3 dB Average Peak GainA 78.8-92.8 GHz 4-bit (16 phases) digitally controlled vector modulator active phase shifter has been designed and implemented in 28nm FDSOI CMOS by STMicroelectronics. The phase shifter exploits a novel IQ generator based on a cascode amplifier incorporating a lumped element coupled line quadrature coupler to generate the in-phase (I) and quadrature (Q) signals. The phase shifter consumes 18 mA from a 1.2 V supply. The measured performances are: average gain of 2.3 dB at 87.4 GHz (between 3.2 and -1.6 dB for the 16 phase states) and -3 dB bandwidth (B 3dB ) from 78.8 to 92.8 GHz; RMS gain error equal to 1.68 dB at 87.4 GHz and lower than 2 dB in the B 3dB ; RMS phase error equal to 9.4 o at 87.4 GHz and lower than 11.9 o in the B 3dB ; S 11 lower than -10.5 dB in the B 3dB ; average input referred 1 dB compression point of -7 dBm (between -8 and -5 dBm for the 16 phase states); average noise figure equal to 10.8 dB at 87 GHz (between -9 and -12 dB for the 16 phase states).ESSCIRC201510.1109/ESSCIRC.2015.7313829https://ieeexplore.ieee.org/document/7313829
Dithered Multi-Bit Sigma-Delta Modulator Based DPWM for DC-DC ConvertersMulti-bit sigma-delta based digital pulse width modulators (DPWM) are used in the control of DC-DC converters in order to achieve high resolution and therefore high output voltage accuracy at switching frequencies up to multiple MHz. The standard sigma-delta modulators which have mainly been used in these DPWMs to date generate idle tones in the applied duty cycle which result in large oscillations in the output voltage. A dithered sigma-delta modulator is instead implemented here which eliminates these oscillations in the output voltage by adding a random signal before the quantizer in the sigma-delta modulator. The power spectral density of the duty cycle produced by the dithered sigma-delta modulator based DPWM shows a reduction in the undesirable idle tones and this is also verified experimentally using a buck converter prototype.Mooney J. et al, APEC201510.1109/APEC.2015.7104752https://ieeexplore.ieee.org/document/7104752
Robust Analysis and Synthesis Design Tools for Digitally Controlled Power Converters”A new suite of Matlab-compatible robust analysis and synthesis design tools for digitally-controlled switched-mode power supplies has been developed. The objective of developing this tool suite is to assist control engineers to design and/or assess digital compensators that are robustly stable. The tool suite comprises of nonlinear, linearized and discrete-time continuous conduction mode and discontinuous conduction mode models, robust analysis algorithms and robust synthesis algorithms. To promote ease of use and adoption, a front-end graphical user interface has also been developed.Halton M. et alAPEC201510.1109/APEC.2015.7104369https://ieeexplore.ieee.org/document/7104369
A 1V 2mW 17GHz Multi-Modulus Frequency Divider Based on TSPC Logic Using 65nm CMOSWe present a multi-modulus frequency divider based upon novel dual-modulus 4/5 and 2/3 true single-phase clocked (TSPC) prescalers. High-speed and low-power operation was achieved by merging the combinatorial counter logic with the flip-flop stages and removing circuit nodes at the expense of allowing a small short-circuit current during a short fraction of the operation cycle, thus minimizing the amount of nodes in the circuit. The divider is designed for operation in wireline or fibre-optic serial link transceivers with programmable divider ratios of 64, 80, 96, 100, 112, 120 and 140. The divider is implemented as part of a phase-locked loop around a quadrature voltage controlled oscillator in a 65nm CMOS technology. The maximum operating frequency is measured to be 17GHz with 2mW power consumption from a 1.0V supply voltage, and occupies 25×50?m 2Ossieur P., et alESSCIRC201410.1109/ESSCIRC.2014.6942114https://ieeexplore.ieee.org/document/6942114
0.3–4.3 GHz Frequency-Accurate Fractional-N Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital ?-? Modulator-Based Divider ControllerIf the modulus of the digital delta-sigma modulator (D??M) in a fractional- N frequency synthesizer is a power of two, then the output frequency is constrained to be a rational multiple of the phase detector frequency (f PD ), where the denominator of the rational multiplier is a power of two. If the required output frequency is not related to f PD in this way, one is forced to approximate the ratio by using a small programmable modulus D??M or a very large power-of-two modulus. Both of these solutions involve additional hardware. Furthermore, the programmable modulus solution can suffer from spurs, while the large power of two lacks accuracy. This paper presents a new solution, based on mixed-radix algebra, where the required ratio is formed by combining two different moduli. The programmable modulus solves the accuracy problem, while the large power-of-two modulus minimizes the spur content. In addition, the phase detector can be clocked at high speed. This paper explains the theoretical foundations of the method, elaborates a design methodology, and presents measured results for an 0.18 ?m SiGe BiCMOS prototype. Kennedy M., et alJSSC201410.1109/JSSC.2014.2322095https://ieeexplore.ieee.org/document/6822651
Scalable Digital Power Controller with Phase Alignment and Frequency SynchronizationThe trend in next-generation switched-mode power supplies will lead to modular, scalable solutions which deliver power efficiently over a wide range of operation. This paper details a new approach to introduce more advanced control features like phase-alignment and frequency synchronization into such scalable solutions. While these methods have been incorporated into multi-phase converters in the past, they all require the distribution of information among the individual converters. In distributed solutions, dedicated communication signals have been used to share this information. An advantage of the proposed method is that it does not require such communication signals between the individual power supplies and is therefore fully scalable and cost effective. Perturbances generated by the switching actions of the individual converters on the common input/output voltage are used by each converter to harvest information about the switching actions of its counterparts. An algorithm is proposed to align the individual phases and synchronize the switching frequencies based on this information. This allows a reduction of input/output capacitor ripple currents, similar to techniques used in multi-phase designs. Experimental results for an FPGA prototype implementation are presented. Effler S., et alTCAS-I201410.1109/TCSI.2013.2283694https://ieeexplore.ieee.org/document/6628004
An inductorless linear optical receiver for 20Gbaud/s (40Gb/s) PAM-4 modulation using 28nm CMOSThis paper 1 presents a linear optical receiver designed using a 28nm CMOS technology suitable for 20Gbaud/s (40Gb/s) PAM-4 modulation. The optical receiver consists of a transimpedance amplifier (gain adjustable from 40dB? to 56dBO) followed by a variable gain amplifier (gain adjustable from 6dB to 17dB). Capacitive peaking is used to achieve a bandwidth of ~10GHz, thus avoiding the use of on-chip inductors which require large die area. A robust automatic gain control loop is used to ensure a constant differential output voltage swing of ~100mV for an input dynamic range of 20?A to 500?A (peak current). Over this same range, high linearity (total harmonic distortion less than 5%, 250MHz sinewave, 10harmonics taken into account) is obtained. The rms input referred noise current (integrated from 10MHz to 20GHz) was 2.5?A rms . The linear optical receiver consumes 56mW from a 1.5V supply voltage. N.A. Quadir, et alISCAS201410.1109/ISCAS.2014.6865674https://ieeexplore.ieee.org/document/6865674
A 10Gb/s Linear Burst-Mode Receiver in 0.25um SiGe:C BiCMOSThis paper presents a 10 Gb/s burst-mode receiver (BMRx) that was designed to have high linearity over a >; 20 dB (optical power) dynamic range. Such a linear BMRx (LBMRx) enables electronic dispersion compensation or multilevel modulation formats in bursty optical links. The LBMRx consists of a variable-gain transimpedance amplifier and a variable-gain post-amplifier. A gain from 47 dB? to 85 dB? was achieved on a single die. Fast (<; 50ns) gain adjustment is achieved using replica based, feedforward automatic gain control and peak detectors, which are reset between bursts using an external reset signal. A sensitivity of - 23.2 dBm at a bit-error rate of 1.1 × 10 -3 was measured using a PIN photodiode. A 0.5 dB penalty is incurred if a 0 dBm burst precedes the burst under consideration; hence the LBMRx can support a dynamic range of 22.7 dB. A 150 ns preamble was used, the guard time between bursts was 25.6 ns. Total harmonic distortion (at 250 MHz) less than 5% was measured for an optical power ranging from - 25 dBm to 0 dBm. The chip was designed in a 0.25 ?m SiGe:C BiCMOS technology, has an area of 2.4 × 2.1 mm 2 and consumes 650 mW from 2.5 V/3.3 V supplies.JSSC201310.1109/JSSC.2012.2221211https://ieeexplore.ieee.org/document/6363488
High Speed, High Accuracy Fractional-N Frequency Synthesizer using Nested Mixed-Radix Digital Sigma-Delta ModulatorsIf the modulus of the D??M in a fractional-N frequency synthesizer is a power of two, then the output frequency is constrained to be a rational multiple of the phase detector frequency (f PD ), where the denominator of the rational multiplier is a power of two. If the required output frequency is not related to f PD in this way, one is forced to approximate the ratio by using a small programmable modulus D??M or a very large power of two modulus. Both solutions involve additional hardware. In addition, the programmable modulus solution can suffer from spurs, while the large power of two lacks accuracy. This paper presents a new solution, based on mixed-radix algebra, where the required ratio is formed by combining two different moduli. The programmable modulus solves the accuracy problem, while the large power of two modulus minimizes the spur content. In addition, the phase detector can be clocked at high speedKennedy M., et al., ESSCIRC201310.1109/ESSCIRC.2013.6649118https://ieeexplore.ieee.org/document/6649118
Application-Specific Instruction-Set Processor for Control of Multi-Rail DC-DC Converter SystemsConventional digital signal processor (DSP) based digital controllers are not specifically optimized for multi-rail DC-DC converter applications. A new application-specific instruction-set processor (ASIP) that overcomes the shortcomings of existing controllers has thus been designed, implemented, and evaluated. The proposed dual multiply-accumulate (MAC) architecture has been implemented using a field programmable gate array and verified in a closed-loop power converter system. The benefits of the proposed ASIP are illustrated through a comparison with a conventional single MAC processor architecture. Experimental results demonstrate improved output voltage transient response compared with existing DSP-based controllers when controlling multiple DC-DC converters. In the case of multiple converters that have a non-integer switching frequency ratio more significant improvements in transient response are obtained due to the processor's interrupt controller.Mooney J., et alTCAS-1201310.1109/TCSI.2012.2215783https://ieeexplore.ieee.org/document/6298055
Efficient Bi-directional Digital Communication Scheme for Isolated Switch Mode Power ConvertersAn efficient high-speed bi-directional data transmission scheme for isolated AC-DC and DC-DC switched mode power converters is presented. The bi-directional scheme supports fast, efficient and reliable transmission of digitally encoded data across the isolation barrier and enables primary side control, allowing effective start-up and a simple interface to system controllers. Another key feature is that the bi-directional communication is independent of coupler gain and degradation and only the minimum number of couplers is required. The digital interface can also be used to transmit auxiliary signals between both sides. For test purposes, the scheme has been implemented on FPGAs and verified using a custom-built SMPC board.Scharrer M., et alTCAS-1201210.1109/TCSI.2012.2206450https://ieeexplore.ieee.org/document/6280602

 


 

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