Our Smart Gate Driver research programme will focus on the development of gate driver solutions for multi-level topologies which naturally reduce the size, cost and weight of the power passive components in systems by 4-9X. We will focus on the design and integration of a number of innovative intelligent gate driver features to enhance, switching speed, EMI, efficiency and performance. New techniques for achieving magnetic galvanic isolation between the low side drive signal and the high-side switch or bridge-driver with the smallest possible transformer size will be incorporated. There will be a focus on achieving very low, gate driver output-to-input common-mode injection immunity (CMTI, CIO) to protect the complex low voltage CMOS control system from the high dV/dt switching node .

We will research novel gate driver secondary side biasing systems to enable miniaturisation and accommodate the addition of new switch control and protection telemetry features required for switches and switch stacks in multi-level architectures. Resonant gate driver energy recovery techniques will be investigated. The gate driver technology will be applicable for vertical DMOS, GaN HEMT or emerging SiC MOSFET. For MCCI, this opens up the prospect of R&D partnerships with a new range of Irish based companies involved in power systems and semiconductor devices for rapidly growing areas such as automotive EV and renewable energy integration.

This project was allocated funding following the MCCI call for proposals for research into innovative future technology solutions in the area of microelectronics. The centre awarded over €5 million in funding to eight MCCI researchers for research into deeptech microelectronic solutions such as beyond 5G wireless communications, implantable biomedical devices, IoT, space and satellite electronics, and sustainable electronics.

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