We’re delighted for Subhash Chevella and Anthony Wall who occupy first and third spots for most popular papers for IEEE Solid-State Circuits Letters.
An impressive achievement for our technology centre.
Subhash Chevella’s Paper “ A Low-Power 1-V Supply Dynamic Comparator”
This letter presents a low-power dynamic comparator for ultralow power applications. The prototype is designed in a 65-nm CMOS process with a supply voltage of 1 V and is compared against the widely used double tail latch comparator in terms of power consumption and input referred rms noise. The addition of cross-coupled devices to the input differential pair prevents the comparator internal nodes from fully discharging to ground in contrast to the conventional architecture. This reduces the power consumption while achieving similar noise levels. Measurements demonstrate that the proposed comparator achieves an input referred rms noise voltage of 220 μV against 210 μV for the conventional comparator with a 30% reduction in power. The proposed circuit consumes 0.19-pJ energy per comparison.
Can be view Here https://ieeexplore.ieee.org/document/9141323
Anthony’s Paper “An Improved Linearity Ring Oscillator-Based Current-to-Digital Converter”
Many biosensors produce single-ended current outputs. Lab-on-chip applications demand parallel readout channels requiring low area current-to-digital converters. High HD2 has limited the current controlled ring oscillator’s (CCROs) adoption as a low area, single-ended converter. This work improves CCRO open loop linearity by 10 dB. A wide-bandwidth current buffer is also designed. A low area (0.0025 mm 2 ), low power ( 357 μW ), single-ended, and 1 MHz bandwidth converter suitable for array readout is presented with the measured performance.
Can be read here https://ieeexplore.ieee.org/document/9854922